RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has support for AXI-Stream IP with Single Master and Single Slave Template. The user can code the Hardware Accelerator in TL-Verilog/Verilog/System Verilog and use this flow to automatically package into an IP and creat…
☆21Feb 25, 2023Updated 3 years ago
Alternatives and similar repositories for RPHAX
Users that are interested in RPHAX are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.☆41Jul 3, 2023Updated 3 years ago
- This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…☆277Apr 25, 2026Updated 5 months ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆103Apr 25, 2026Updated 5 months ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆16Jan 14, 2021Updated 5 years ago
- A library and command-line tool for querying a Verilog netlist.☆30Jun 13, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 3 years ago
- GUI editor for hardware description designs☆30Sep 14, 2026Updated last month
- ☆26Feb 15, 2025Updated last year
- ☆21Updated this week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆68Dec 19, 2021Updated 4 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 5 years ago
- VHDL plugin for RgGen☆15Jul 1, 2026Updated 3 months ago
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆13Aug 12, 2020Updated 6 years ago
- An overview of TL-Verilog resources and projects☆91Apr 25, 2026Updated 5 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆10Nov 2, 2023Updated 2 years ago
- Repository for VSD-IAT Workshop: Physical Verification using SKY130☆10Aug 15, 2021Updated 5 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆258Sep 24, 2026Updated 2 weeks ago
- Recursive unified ORAM☆15Sep 23, 2015Updated 11 years ago
- Collection of simple interfaces for Digilent Pmods☆13Aug 3, 2023Updated 3 years ago
- ☆65Nov 9, 2021Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆64Jul 9, 2021Updated 5 years ago
- FPU Double VHDL☆12Jul 17, 2014Updated 12 years ago
- Virtual Breadboard / PCB simulation for Prototyping and Educational Purposes☆16Jun 4, 2023Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This is a SpyDrNet Plugin for a physical design related transformations☆16Sep 22, 2026Updated 3 weeks ago
- This repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primar…☆45Mar 28, 2022Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆36Dec 10, 2021Updated 4 years ago
- An HBM FPGA based SpMV Accelerator☆19Aug 29, 2024Updated 2 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆87Oct 28, 2023Updated 2 years ago
- ☆23Feb 15, 2013Updated 13 years ago
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- ☆14Apr 13, 2025Updated last year
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆163Oct 31, 2024Updated last year
- ☆11Jan 25, 2023Updated 3 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 3 years ago
- This project is made to generate Polar decoders (unrolled decoders).☆15May 31, 2025Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43May 24, 2020Updated 6 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆56Dec 26, 2023Updated 2 years ago
- ☆21Sep 23, 2026Updated 3 weeks ago