shariethernet / RPHAXView external linksLinks
RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has support for AXI-Stream IP with Single Master and Single Slave Template. The user can code the Hardware Accelerator in TL-Verilog/Verilog/System Verilog and use this flow to automatically package into an IP and creat…
☆21Feb 25, 2023Updated 2 years ago
Alternatives and similar repositories for RPHAX
Users that are interested in RPHAX are comparing it to the libraries listed below
Sorting:
- This is a SpyDrNet Plugin for a physical design related transformations☆16Jun 13, 2025Updated 8 months ago
- This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…☆237Jun 11, 2025Updated 8 months ago
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆13Aug 12, 2020Updated 5 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- GUI editor for hardware description designs☆30Jul 11, 2023Updated 2 years ago
- This repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primar…☆12Mar 28, 2022Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆19Sep 19, 2023Updated 2 years ago
- ☆10Nov 2, 2023Updated 2 years ago
- Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.☆40Jul 3, 2023Updated 2 years ago
- ☆19Dec 22, 2025Updated last month
- SPICE netlist visualizer☆83Jan 2, 2026Updated last month
- Online documentation can be found at https://minres.github.io/SCViewer/☆21Feb 11, 2024Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42May 24, 2020Updated 5 years ago
- ☆24Feb 15, 2013Updated 12 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Dec 26, 2023Updated 2 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆47Mar 11, 2024Updated last year
- Contains examples to start with Kactus2.☆23Aug 5, 2024Updated last year
- ☆20Jun 18, 2022Updated 3 years ago
- An overview of TL-Verilog resources and projects☆82Dec 22, 2025Updated last month
- ☆27Feb 15, 2025Updated 11 months ago
- mRNA☆26Mar 16, 2021Updated 4 years ago
- Hardware implementation of ORAM☆24Jul 12, 2017Updated 8 years ago
- CMake based hardware build system☆35Jan 30, 2026Updated 2 weeks ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 4 years ago
- ☆11May 31, 2016Updated 9 years ago
- Artifacts for the SCVP lecture☆11Nov 17, 2021Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Dec 19, 2021Updated 4 years ago
- ☆97Dec 31, 2025Updated last month
- Demo SoC for SiliconCompiler.☆62Jan 28, 2026Updated 2 weeks ago
- ☆64Nov 9, 2021Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated last year
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆29Updated this week
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆36Jun 17, 2025Updated 7 months ago
- Hardware Security Labs☆31May 3, 2017Updated 8 years ago
- ☆33Nov 6, 2024Updated last year
- ☆31Oct 2, 2023Updated 2 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago