shariethernet / RPHAX
RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has support for AXI-Stream IP with Single Master and Single Slave Template. The user can code the Hardware Accelerator in TL-Verilog/Verilog/System Verilog and use this flow to automatically package into an IP and creat…
☆17Updated 2 years ago
Alternatives and similar repositories for RPHAX:
Users that are interested in RPHAX are comparing it to the libraries listed below
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated last month
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated last year
- ☆25Updated 2 weeks ago
- ☆20Updated 3 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆38Updated 3 years ago
- APB UVC ported to Verilator☆11Updated last year
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆46Updated this week
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last week
- SystemVerilog RTL Linter for YoSys☆20Updated 4 months ago
- Implementing Different Adder Structures in Verilog☆64Updated 5 years ago
- Open Source PHY v2☆27Updated 11 months ago
- Open source ISS and logic RISC-V 32 bit project☆43Updated 4 months ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆29Updated last year
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆15Updated 3 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆67Updated this week
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- ☆40Updated 3 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- ☆36Updated 2 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago