os-fpga / 1st-CLaaS
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
☆199Updated 3 weeks ago
Alternatives and similar repositories for 1st-CLaaS:
Users that are interested in 1st-CLaaS are comparing it to the libraries listed below
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆234Updated 3 weeks ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆202Updated 4 years ago
- Open-source FPGA research and prototyping framework.☆204Updated 7 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆133Updated 6 months ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆210Updated 5 years ago
- Random ideas and interesting ideas for things we hope to eventually do.☆86Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆172Updated 8 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆100Updated 5 years ago
- Connectal is a framework for software-driven hardware development.☆166Updated last year
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆270Updated this week
- OpenSoC Fabric - A Network-On-Chip Generator☆164Updated 4 years ago
- A utility for Composing FPGA designs from Peripherals☆175Updated 3 months ago
- ☆246Updated 2 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆280Updated this week
- VeeR EL2 Core☆269Updated last week
- Build Customized FPGA Implementations for Vivado☆308Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆223Updated 4 months ago
- The OpenPiton Platform☆677Updated 3 weeks ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆366Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆221Updated last year
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆134Updated 3 years ago
- An Open-Source Design and Verification Environment for RISC-V☆79Updated 3 years ago
- Basic RISC-V CPU implementation in VHDL.☆165Updated 4 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆363Updated 3 weeks ago
- A directory of Western Digital’s RISC-V SweRV Cores☆863Updated 5 years ago
- Recipe for FPGA cooking☆293Updated 6 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆248Updated 3 weeks ago
- RISC-V Formal Verification Framework☆598Updated 2 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆322Updated 3 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆157Updated 2 months ago