Alternatives and similar repositories for 1st-CLaaS

Users that are interested in 1st-CLaaS are comparing it to the libraries listed below

• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆238Updated 2 months ago
• f4pga / ideas
  Random ideas and interesting ideas for things we hope to eventually do.
  ☆87Updated 3 years ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆203Updated 4 years ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆208Updated 11 months ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆137Updated 2 years ago
• openpower-cores / a2i
  ☆247Updated 2 years ago
• dawsonjon / Chips-2.0
  FPGA Design Suite based on C to Verilog design flow.
  ☆245Updated 6 years ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆292Updated last week
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆171Updated last week
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆225Updated last year
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆329Updated this week
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆171Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆178Updated 2 months ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆181Updated 7 months ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆213Updated 5 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆88Updated 5 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆140Updated 10 months ago
• jhallen / vivado_setup
  How to set up Xilinx Vivado for source control
  ☆105Updated 10 months ago
• phanrahan / magma
  magma circuits
  ☆261Updated 9 months ago
• cornell-brg / pymtl
  Python-based hardware modeling framework
  ☆242Updated 5 years ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆227Updated this week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆263Updated last month
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆160Updated last month
• vmware-archive / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆446Updated 4 years ago
• stanford-ppl / spatial
  Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
  ☆282Updated last year
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆392Updated 9 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆146Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago