os-fpga / 1st-CLaaSLinks
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
☆205Updated 3 weeks ago
Alternatives and similar repositories for 1st-CLaaS
Users that are interested in 1st-CLaaS are comparing it to the libraries listed below
Sorting:
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆240Updated 4 months ago
- Open-source FPGA research and prototyping framework.☆208Updated last year
- FPGA Design Suite based on C to Verilog design flow.☆246Updated 6 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆447Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Random ideas and interesting ideas for things we hope to eventually do.☆86Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 9 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated last year
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆215Updated 5 years ago
- ☆247Updated 3 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆180Updated last week
- Python-based hardware modeling framework☆244Updated 5 years ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆202Updated 4 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- magma circuits☆262Updated 11 months ago
- Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"☆284Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆268Updated 3 weeks ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆294Updated this week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- How to set up Xilinx Vivado for source control☆108Updated last year
- 😎 A curated list of awesome RISC-V implementations☆138Updated 2 years ago
- Open source machine learning accelerators☆387Updated last year
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆289Updated last week
- Basic RISC-V CPU implementation in VHDL.☆169Updated 5 years ago
- A 32-bit RISC-V soft processor☆315Updated 2 months ago
- Build Customized FPGA Implementations for Vivado☆341Updated last week
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆226Updated last week
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆253Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- A configurable RTL to bitstream FPGA toolchain☆45Updated last week