os-fpga / 1st-CLaaS
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
☆198Updated 5 months ago
Alternatives and similar repositories for 1st-CLaaS:
Users that are interested in 1st-CLaaS are comparing it to the libraries listed below
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆232Updated last month
- Open-source FPGA research and prototyping framework.☆199Updated 5 months ago
- An abstraction library for interfacing EDA tools☆655Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆240Updated 3 weeks ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆202Updated 4 years ago
- A utility for Composing FPGA designs from Peripherals☆170Updated 3 weeks ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆209Updated 4 years ago
- Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"☆274Updated 7 months ago
- Build Customized FPGA Implementations for Vivado☆300Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆163Updated 5 months ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆276Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆220Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆264Updated this week
- magma circuits☆255Updated 2 months ago
- A Linux-capable RISC-V multicore for and by the world☆647Updated this week
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆103Updated 6 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆134Updated 2 years ago
- Random ideas and interesting ideas for things we hope to eventually do.☆86Updated 2 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆537Updated last week
- VeeR EL2 Core☆257Updated this week
- How to set up Xilinx Vivado for source control☆101Updated 4 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆219Updated last year
- ☆220Updated 2 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆437Updated 3 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆203Updated this week
- FPGA Design Suite based on C to Verilog design flow.☆238Updated 5 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆98Updated 5 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆130Updated 3 months ago
- Connectal is a framework for software-driven hardware development.☆163Updated last year