xzlashutosh / avsddac_3v3Links
This repository contains the design and simulation process and results of potentiometric digital to analog converter.
☆15Updated 5 years ago
Alternatives and similar repositories for avsddac_3v3
Users that are interested in avsddac_3v3 are comparing it to the libraries listed below
Sorting:
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- Open Analog Design Environment☆24Updated 2 years ago
- Completed LDO Design for Skywaters 130nm☆17Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A current mode buck converter on the SKY130 PDK☆31Updated 4 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 9 months ago
- ☆38Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- ☆43Updated 3 years ago
- FPGA250 aboard the eFabless Caravel☆31Updated 4 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- ☆14Updated 2 years ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆19Updated 4 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 11 months ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆14Updated 7 months ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆20Updated 4 years ago
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Updated 4 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Updated 4 years ago
- Skywater 130nm Klayout Device Generators PDK☆31Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆14Updated 4 years ago
- ☆38Updated 11 months ago
- Zero to ASIC group submission for MPW2☆13Updated 7 months ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆48Updated 7 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated last week