Alternatives and similar repositories for picorv

Users that are interested in picorv are comparing it to the libraries listed below

• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆60Updated last month
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 9 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆98Updated last week
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 3 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆66Updated this week
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆63Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 6 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆97Updated 2 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆85Updated 2 weeks ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆81Updated 5 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆80Updated 3 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆23Updated 2 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 4 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated 2 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆30Updated 4 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆31Updated 9 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated 3 weeks ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 3 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 3 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆39Updated last year