clairexen / picorvLinks
PicoRV
☆44Updated 5 years ago
Alternatives and similar repositories for picorv
Users that are interested in picorv are comparing it to the libraries listed below
Sorting:
- System on Chip toolkit for Amaranth HDL☆92Updated 10 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Naive Educational RISC V processor☆87Updated last month
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- User-friendly explanation of Yosys options☆114Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 3 years ago
- ☆23Updated 3 months ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆105Updated last week
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 6 years ago
- Mutation Cover with Yosys (MCY)☆86Updated 2 weeks ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Demo SoC for SiliconCompiler.☆60Updated this week
- Experiments with Yosys cxxrtl backend☆49Updated 7 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated 3 weeks ago
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆91Updated 5 years ago
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated this week
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- Xilinx Unisim Library in Verilog☆84Updated 5 years ago
- ☆38Updated 3 years ago