atthecodeface / cdl_hardwareLinks
CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc
☆16Updated 5 years ago
Alternatives and similar repositories for cdl_hardware
Users that are interested in cdl_hardware are comparing it to the libraries listed below
Sorting:
- A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores☆17Updated 6 months ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆15Updated 10 months ago
- ☆14Updated 4 years ago
- RISCV implementation in Verilog (RV32I spec)☆16Updated 4 years ago
- RISC5Verilog for Pipistrello using lpddr memory☆12Updated 5 years ago
- A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores☆23Updated 10 months ago
- RISC-V soft core running on Colorlight 5B-74B.☆31Updated 4 years ago
- basic example of litex on colorLight 5A-75B based on fpga_101/lab004☆33Updated 2 years ago
- "Okiedokie" by Soopadoopa☆13Updated 4 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆46Updated 10 months ago
- Multi-Probe SWR/PWR Meter with Icom Tuner handling for Yaesu Rigs☆9Updated 7 years ago
- "Oscar's Chair" by Fizzer☆15Updated 4 years ago
- Amoeba by Excess☆17Updated 3 years ago
- Carrito (Spanish for Small car) a home brewed arduino controled car.☆9Updated 6 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Updated 6 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆77Updated 2 years ago
- Opensource building blocks for TinyFPGA microcontrollers and retro computers.☆17Updated 7 years ago
- Port of Amber ARM Core project to Marsohod2 platform☆13Updated 5 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆73Updated 2 years ago
- Noir Computer☆16Updated last year
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 6 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆87Updated 5 years ago
- This implementation of file system is developed by ELM Chan☆16Updated 4 months ago
- Hardware random number generator for FPGAs☆10Updated 10 years ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- A 6800 CPU written in nMigen☆49Updated 4 years ago
- Learn how to create your own 32-bit system from scratch.☆13Updated 3 years ago
- Simulation of the classic Pacman arcade game on a PanoLogic thin client.☆34Updated 5 years ago