atthecodeface / cdl_hardwareLinks
CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc
☆16Updated 5 years ago
Alternatives and similar repositories for cdl_hardware
Users that are interested in cdl_hardware are comparing it to the libraries listed below
Sorting:
- A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores☆18Updated 2 months ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆15Updated last year
- ☆14Updated 4 years ago
- RISCV implementation in Verilog (RV32I spec)☆16Updated 4 years ago
- RISC-V soft core running on Colorlight 5B-74B.☆34Updated 4 years ago
- "Okiedokie" by Soopadoopa☆13Updated 5 years ago
- A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores☆23Updated last year
- The winning Assembly Summer 2015 4k intro by Prismbeings.☆20Updated 9 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆46Updated last year
- Amoeba by Excess☆17Updated 3 years ago
- basic example of litex on colorLight 5A-75B based on fpga_101/lab004☆34Updated 2 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite …☆77Updated 2 years ago
- "Oscar's Chair" by Fizzer☆15Updated 5 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆75Updated 2 years ago
- "Terrarium" by Fizzer☆15Updated 5 years ago
- Apollo CPU Core in Verilog. For learning and having fun with open FPGA☆44Updated 8 years ago
- ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts☆39Updated 4 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Basic RISC-V CPU implementation in VHDL.☆169Updated 4 years ago
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆86Updated 5 years ago
- Unofficial Yosys WebAssembly packages☆71Updated this week
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Updated 6 years ago
- Exploring gate level simulation☆58Updated 4 months ago
- A 6800 CPU written in nMigen☆49Updated 4 years ago
- ☆55Updated 2 years ago
- A collection of little open source FPGA hobby projects☆50Updated 5 years ago
- 😎 A curated list of awesome RISC-V implementations☆138Updated 2 years ago
- This is a higan/Verilator co-simulation example/framework☆50Updated 7 years ago