Alternatives and similar repositories for cdl_hardware

Users that are interested in cdl_hardware are comparing it to the libraries listed below

• klessydra / T03x
  A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores
  ☆18Updated 5 months ago
• Saanlima / RISC5Verilog_psram
  ☆15Updated 4 years ago
• klessydra / F03x
  A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance
  ☆15Updated last year
• zxmarcos / riscado-v
  RISCV implementation in Verilog (RV32I spec)
  ☆16Updated last month
• ghent360 / riscvOnColorlight-5A-75B
  RISC-V soft core running on Colorlight 5B-74B.
  ☆37Updated 4 years ago
• klessydra / T02x
  A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores
  ☆23Updated last year
• demoscene-source-archive / okiedokie
  "Okiedokie" by Soopadoopa
  ☆13Updated 5 years ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆44Updated last year
• trabucayre / litexOnColorlightLab004
  basic example of litex on colorLight 5A-75B based on fpga_101/lab004
  ☆36Updated 2 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆54Updated 7 years ago
• armak / Hydrokinetics
  The winning Assembly Summer 2015 4k intro by Prismbeings.
  ☆21Updated 9 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆78Updated 3 years ago
• excess-demogroup / amoeba
  Amoeba by Excess
  ☆17Updated 3 years ago
• demoscene-source-archive / oscar-s-chair
  "Oscar's Chair" by Fizzer
  ☆15Updated 5 years ago
• Obijuan / ACC
  Apollo CPU Core in Verilog. For learning and having fun with open FPGA
  ☆44Updated 9 years ago
• demoscene-source-archive / world-domination
  World Domination by ODD
  ☆18Updated 14 years ago
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆49Updated 4 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆90Updated 6 years ago
• skiphansen / pano_man
  Simulation of the classic Pacman arcade game on a PanoLogic thin client.
  ☆34Updated 6 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆54Updated 4 years ago
• DoctorWkt / ULX3S-Blinky
  A blinky project for the ULX3S v3.0.3 FPGA board
  ☆17Updated 6 years ago
• ulx3s / ulx3s-toolchain
  ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts
  ☆39Updated 5 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆45Updated 3 years ago
• Wren6991 / NorForkConditionally
  What's the simplest CPU you can build?
  ☆35Updated 11 years ago
• mattvenn / wokwi-verilog-gds-test
  ☆55Updated 3 years ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆87Updated 6 years ago
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆45Updated last year
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆74Updated this week
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆76Updated 2 years ago
• lawrie / ulx3s_zx_spectrum
  Minimal ZX Spectrum for Ulx3s ECP5 board
  ☆12Updated 5 years ago