Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
☆99Apr 25, 2026Updated 3 months ago
Alternatives and similar repositories for RISC-V_MYTH_Workshop
Users that are interested in RISC-V_MYTH_Workshop are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆87Oct 28, 2023Updated 2 years ago
- This repository is created for conducting RISC-V 5-day workshops☆23Jul 29, 2020Updated 5 years ago
- An overview of TL-Verilog resources and projects☆89Apr 25, 2026Updated 3 months ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Feb 25, 2023Updated 3 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆84Nov 26, 2020Updated 5 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆251Updated this week
- Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.☆41Jul 3, 2023Updated 3 years ago
- CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc☆17Feb 20, 2020Updated 6 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆16Jan 14, 2021Updated 5 years ago
- This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…☆269Apr 25, 2026Updated 3 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- ☆41Feb 28, 2022Updated 4 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆126Jul 31, 2021Updated 4 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆17Oct 16, 2021Updated 4 years ago
- RISCV implementation in Verilog (RV32I spec)☆18Nov 5, 2025Updated 8 months ago
- A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores☆19Jul 4, 2025Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆34Aug 28, 2023Updated 2 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆51Aug 24, 2024Updated last year
- Flat Shade Society - Solskogen 2019 invite☆10Oct 2, 2019Updated 6 years ago
- "Okiedokie" by Soopadoopa☆14Aug 22, 2020Updated 5 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆20Aug 19, 2024Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆26Aug 12, 2022Updated 3 years ago
- ☆16Jan 12, 2021Updated 5 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated last year
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆49Dec 6, 2020Updated 5 years ago
- Source for the PlayStation 2 demo "4 Edges" by The Black Lotus☆10Jul 23, 2016Updated 10 years ago
- ☆14Apr 13, 2025Updated last year
- Understand how TCL scripting automates ASIC synthesis and timing analysis using Yosys & OpenTimer, with CSV/Excel inputs acting as fr…☆19Oct 26, 2025Updated 8 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆35Dec 10, 2021Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Initial implementation utilising AARNN principles☆10Feb 27, 2023Updated 3 years ago
- Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications☆214Apr 25, 2026Updated 3 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 6 years ago
- MR1 formally verified RISC-V CPU☆59Dec 16, 2018Updated 7 years ago
- USB1.1 Host Controller + PHY☆18Aug 4, 2021Updated 4 years ago
- Collection of simple interfaces for Digilent Pmods☆13Aug 3, 2023Updated 2 years ago
- The winning Assembly Summer 2015 4k intro by Prismbeings.☆22Jun 29, 2016Updated 10 years ago