cornell-brg / lizard

Related projects: ⓘ

• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆43Updated 3 weeks ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 2 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆76Updated last month
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆92Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆80Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆57Updated 5 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆148Updated 4 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆58Updated 3 weeks ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 3 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆105Updated last month
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆66Updated 4 months ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆72Updated 5 years ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆33Updated 2 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆65Updated 4 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆84Updated 4 months ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆78Updated 8 months ago
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆66Updated last year
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆61Updated 4 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆50Updated 5 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆83Updated 5 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆76Updated 4 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆95Updated last week
• sifive / fpga-shells
  ☆132Updated 2 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 4 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆135Updated 2 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆55Updated this week
• riscv / riscv-test-env
  ☆40Updated 3 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆76Updated 2 weeks ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆118Updated 6 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆82Updated 8 months ago