cornell-brg / lizardLinks
Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
☆88Updated 6 years ago
Alternatives and similar repositories for lizard
Users that are interested in lizard are comparing it to the libraries listed below
Sorting:
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆46Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆163Updated 5 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆75Updated 2 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- Demo SoC for SiliconCompiler.☆61Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 6 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated last year
- Yet Another RISC-V Implementation☆97Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 2 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆95Updated 6 months ago
- FPGA tool performance profiling☆102Updated last year
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- Open-source FPGA research and prototyping framework.☆208Updated last year
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- FuseSoC standard core library☆147Updated 4 months ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆147Updated last month
- SoC based on VexRiscv and ICE40 UP5K☆160Updated 6 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 4 months ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- A utility for Composing FPGA designs from Peripherals☆184Updated 9 months ago