shivanishah269 / risc-v-core
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
☆75Updated last year
Alternatives and similar repositories for risc-v-core:
Users that are interested in risc-v-core are comparing it to the libraries listed below
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆86Updated last week
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆88Updated 2 months ago
- An overview of TL-Verilog resources and projects☆78Updated last month
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆42Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆57Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆86Updated last year
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆173Updated last week
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆68Updated 4 years ago
- Basic RISC-V Test SoC☆122Updated 6 years ago
- RISC-V Verification Interface☆89Updated 2 months ago
- Open source ISS and logic RISC-V 32 bit project☆52Updated last week
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- A demo system for Ibex including debug support and some peripherals☆63Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆86Updated this week
- FuseSoC standard core library☆134Updated last month
- ☆155Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 2 years ago
- ☆40Updated 3 years ago
- This repository is created for conducting RISC-V 5-day workshops☆22Updated 4 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆42Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆69Updated 2 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 4 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆35Updated 4 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆158Updated last year
- Control and status register code generator toolchain☆130Updated this week
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- OSVVM Documentation☆33Updated this week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆81Updated this week