dovebutch / tlv-comp
☆26Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for tlv-comp
- Small SERV-based SoC primarily for OpenMPW tapeout☆35Updated last year
- ☆22Updated last year
- ☆33Updated last year
- Open Processor Architecture☆26Updated 8 years ago
- ☆36Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- FPGA250 aboard the eFabless Caravel☆27Updated 3 years ago
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- An automatic clock gating utility☆43Updated 4 months ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- LunaPnR is a place and router for integrated circuits☆44Updated this week
- Experiments with fixed function renderers and Chisel HDL☆58Updated 5 years ago
- RISC-V processor☆28Updated 2 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Updated 3 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- Xilinx Unisim Library in Verilog☆71Updated 4 years ago
- A padring generator for ASICs☆22Updated last year
- Bitstream relocation and manipulation tool.☆40Updated last year
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- ☆39Updated 4 years ago
- AXI Formal Verification IP☆19Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆60Updated 3 weeks ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 4 months ago
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- ☆12Updated 3 years ago
- USB virtual model in C++ for Verilog☆28Updated last month
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆20Updated 3 years ago