☆26Feb 15, 2025Updated last year
Alternatives and similar repositories for tlv-comp
Users that are interested in tlv-comp are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆255Aug 27, 2026Updated 3 weeks ago
- Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications☆214Apr 25, 2026Updated 5 months ago
- A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COrouti…☆21Dec 24, 2023Updated 2 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Feb 25, 2023Updated 3 years ago
- Implementation of a cache memory in verilog☆14Dec 5, 2017Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Mirror of tachyon-da cvc Verilog simulator☆58Mar 16, 2026Updated 6 months ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Sep 24, 2021Updated 5 years ago
- OpenRISC 1000 port for sourceware.org's src tree (binutils, gdb, newlib, etc.)☆19Mar 12, 2016Updated 10 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Dec 30, 2022Updated 3 years ago
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- ReconOS - Operating System for Reconfigurable Hardware☆31Feb 4, 2022Updated 4 years ago
- Keras implementation of the multi-channel cascaded architecture introduced in the paper "Brain Tumor Segmentation with Deep Neural Networ…☆23Jan 22, 2018Updated 8 years ago
- GNU Superoptimizer Version 2☆26May 19, 2021Updated 5 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆87Oct 11, 2019Updated 6 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- This is the client side library to access JTAG Server distributed with Quartus (jtagd/jtagserver.exe). The protocol is known as Advanced …☆20Aug 18, 2025Updated last year
- PCB layout for my cheap FPGA HDMI experimenting board☆10Aug 21, 2014Updated 12 years ago
- Open Processor Architecture☆26Apr 7, 2016Updated 10 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- ☆247Aug 12, 2022Updated 4 years ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆26Jun 7, 2021Updated 5 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆49Jul 24, 2024Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆31Jun 22, 2024Updated 2 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Jan 28, 2026Updated 7 months ago
- Web apps for Planck-related stuff☆13Sep 13, 2017Updated 9 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Jul 23, 2026Updated 2 months ago
- ☆12May 15, 2022Updated 4 years ago
- Reconfigurable Binary Engine☆18Mar 23, 2021Updated 5 years ago
- High-Performance Reproducible BLAS using posit arithmetic☆12Mar 16, 2022Updated 4 years ago
- An automated production line visual inspection project for the identification of faults in Coca-Cola bottles leaving a production facilit…☆10Jul 26, 2021Updated 5 years ago
- ☆18May 24, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Modular, flexible, cross-platform workload profiling and characterization☆13Mar 1, 2021Updated 5 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- Past Pixels Camp t-shirt challenges☆13Apr 1, 2019Updated 7 years ago
- nMigen examples for the ULX3S board☆16Nov 30, 2020Updated 5 years ago
- PicoRV☆45Feb 19, 2020Updated 6 years ago
- HW design files for Spresense boards☆38Jun 13, 2024Updated 2 years ago
- Shakti: development platform for PlatformIO☆39May 31, 2022Updated 4 years ago