A 32-bit Microcontroller featuring a RISC-V core
☆161Feb 28, 2018Updated 8 years ago
Alternatives and similar repositories for mriscv
Users that are interested in mriscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A 32-bit RISC-V processor for mriscv project☆60Jul 17, 2017Updated 8 years ago
- A 32-bit Microcontroller for NEXYS4-DDR fpga based on mriscv.☆13Apr 12, 2017Updated 9 years ago
- RISC-V CPU Core☆420Jun 24, 2025Updated 9 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆91Jul 29, 2019Updated 6 years ago
- CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc☆17Feb 20, 2020Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- RISCV implementation in Verilog (RV32I spec)☆18Nov 5, 2025Updated 5 months ago
- An open-source microcontroller system based on RISC-V☆1,023Feb 6, 2024Updated 2 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆976Nov 15, 2024Updated last year
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆372Jul 12, 2017Updated 8 years ago
- ☆12Nov 26, 2024Updated last year
- A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores☆19Jul 4, 2025Updated 9 months ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated this week
- A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores☆24Aug 24, 2024Updated last year
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Xbox demo from 2003☆12Oct 1, 2013Updated 12 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,106Feb 11, 2026Updated 2 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,886Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,092Jun 27, 2024Updated last year
- Using VexRiscv without installing Scala☆39Nov 10, 2021Updated 4 years ago
- A 32-bit RISC-V soft processor☆326Jan 26, 2026Updated 2 months ago
- VeeR EH1 core☆935May 29, 2023Updated 2 years ago
- RISC-V Formal Verification Framework☆629Apr 6, 2022Updated 4 years ago
- Source for the PlayStation 2 demo "4 Edges" by The Black Lotus☆11Jul 23, 2016Updated 9 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- The root repo for lowRISC project and FPGA demos.☆601Aug 3, 2023Updated 2 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆50Aug 24, 2024Updated last year
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆419Updated this week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated last month
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆243Mar 4, 2026Updated last month
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆83Oct 11, 2019Updated 6 years ago
- RADIX-4 SRT division☆12Oct 31, 2019Updated 6 years ago
- Flat Shade Society - Solskogen 2019 invite☆10Oct 2, 2019Updated 6 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆687Jul 16, 2025Updated 8 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆80Oct 1, 2022Updated 3 years ago
- 32-bit Superscalar RISC-V CPU☆1,223Sep 18, 2021Updated 4 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,213May 26, 2025Updated 10 months ago
- "Okiedokie" by Soopadoopa☆15Aug 22, 2020Updated 5 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Dec 10, 2019Updated 6 years ago
- Light-weight RISC-V RV32IMC microcontroller core.☆104Mar 4, 2017Updated 9 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago