Alternatives and similar repositories for mriscv

Users that are interested in mriscv are comparing it to the libraries listed below

• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 6 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆283Updated last year
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆178Updated 10 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆283Updated 5 years ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆172Updated 5 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆404Updated 7 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆258Updated 3 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆91Updated 6 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆60Updated 8 years ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆315Updated 3 weeks ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• FPGAwars / FPGA-peripherals
  Collection of open-source peripherals in Verilog
  ☆183Updated 3 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆134Updated 7 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆161Updated 10 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆321Updated last year
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆301Updated this week
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 6 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• rubund / graywolf
  ☆114Updated 4 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆334Updated last year
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆131Updated 2 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆571Updated 5 months ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆320Updated 2 months ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆147Updated 2 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆167Updated 6 years ago