TL-X-org / TL-V_Projects
An overview of TL-Verilog resources and projects
☆76Updated 2 weeks ago
Alternatives and similar repositories for TL-V_Projects:
Users that are interested in TL-V_Projects are comparing it to the libraries listed below
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆62Updated last week
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆72Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆65Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆55Updated 2 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆65Updated this week
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆81Updated 2 weeks ago
- ☆14Updated last year
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆156Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆182Updated this week
- Fabric generator and CAD tools☆162Updated 3 weeks ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆94Updated 4 years ago
- RISC-V Verification Interface☆85Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago
- Implementation of RISC-V RV32I☆17Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆84Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆67Updated last year
- OpenROAD users should look at this repository first for instructions on getting started☆102Updated 3 years ago
- ☆76Updated 6 months ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆57Updated 11 months ago
- Curriculum for a university course to teach chip design using open source EDA tools☆59Updated last year
- Complete tutorial code.☆17Updated 10 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- Basic RISC-V Test SoC☆118Updated 5 years ago
- This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://ww…☆16Updated 2 years ago