shailja-thakur / VGen
☆149Updated 6 months ago
Alternatives and similar repositories for VGen
Users that are interested in VGen are comparing it to the libraries listed below
Sorting:
- An open-source benchmark for generating design RTL with natural language☆106Updated 6 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆191Updated 3 months ago
- Verilog evaluation benchmark for large language model☆259Updated 3 months ago
- ☆192Updated 10 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆29Updated 6 months ago
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆27Updated 11 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆48Updated 7 months ago
- ☆27Updated 2 months ago
- ☆52Updated 7 months ago
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆13Updated last year
- ☆42Updated 7 months ago
- ☆29Updated 10 months ago
- ☆23Updated last month
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆125Updated 7 months ago
- ☆39Updated last year
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆40Updated 4 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated 2 years ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆42Updated last month
- ☆160Updated 2 months ago
- Collection of digital hardware modules & projects (benchmarks)☆58Updated last week
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆13Updated 11 months ago
- Fix syntax errors of LLM-generated RTL☆29Updated 11 months ago
- ☆80Updated last month
- ☆56Updated last month
- Some useful documents of Synopsys☆72Updated 3 years ago
- HLSyn benchmark for paper "Towards a Comprehensive Benchmark for FPGA Targeted High-Level Synthesis"☆29Updated last year
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆173Updated 5 years ago
- This is a python repo for flattening Verilog☆16Updated this week
- ☆25Updated 3 weeks ago