shailja-thakur / VGen
☆145Updated 6 months ago
Alternatives and similar repositories for VGen:
Users that are interested in VGen are comparing it to the libraries listed below
- An open-source benchmark for generating design RTL with natural language☆103Updated 5 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆183Updated 2 months ago
- Verilog evaluation benchmark for large language model☆250Updated 2 months ago
- ☆183Updated 9 months ago
- ☆41Updated 6 months ago
- ☆26Updated last month
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆27Updated 5 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆45Updated 7 months ago
- ☆52Updated last month
- LLM Evaluation Benchmark on Hardware Formal Verification☆13Updated 3 weeks ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆125Updated 6 months ago
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆25Updated 11 months ago
- ☆138Updated 3 years ago
- ☆22Updated 2 weeks ago
- ☆153Updated last month
- Dataset for ML-guided Accelerator Design☆36Updated 5 months ago
- ☆51Updated 6 months ago
- ☆12Updated 7 months ago
- ☆77Updated 3 weeks ago
- ☆22Updated 2 years ago
- ☆23Updated this week
- HLSyn benchmark for paper "Towards a Comprehensive Benchmark for FPGA Targeted High-Level Synthesis"☆29Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆54Updated 5 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆81Updated last year
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆101Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated last year
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆138Updated 2 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆76Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆197Updated this week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆124Updated this week