shailja-thakur / VGenLinks
☆171Updated 9 months ago
Alternatives and similar repositories for VGen
Users that are interested in VGen are comparing it to the libraries listed below
Sorting:
- An open-source benchmark for generating design RTL with natural language☆121Updated 8 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆210Updated 5 months ago
- Verilog evaluation benchmark for large language model☆288Updated 5 months ago
- ☆217Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆52Updated last month
- ☆52Updated last month
- ☆46Updated 9 months ago
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆27Updated last year
- ☆86Updated 3 weeks ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆130Updated 9 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆34Updated 8 months ago
- ☆24Updated 3 months ago
- ☆65Updated 3 months ago
- ☆175Updated 4 months ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆52Updated 3 months ago
- ☆44Updated last month
- This is a python repo for flattening Verilog☆18Updated 2 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆150Updated 2 months ago
- ☆30Updated 4 months ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆43Updated 7 months ago
- ☆77Updated 3 weeks ago
- ☆105Updated 5 years ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last week
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆180Updated 5 years ago
- EPFL logic synthesis benchmarks☆201Updated last month
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated 4 months ago
- ☆73Updated last month
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆14Updated last year
- ☆14Updated 10 months ago
- ☆150Updated 3 years ago