☆201Oct 17, 2024Updated last year
Alternatives and similar repositories for VGen
Users that are interested in VGen are comparing it to the libraries listed below
Sorting:
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆255Feb 9, 2025Updated last year
- ☆43Oct 17, 2024Updated last year
- Verilog evaluation benchmark for large language model☆378Jul 14, 2025Updated 7 months ago
- An open-source benchmark for generating design RTL with natural language☆162Nov 8, 2024Updated last year
- ☆265Jul 8, 2024Updated last year
- ☆55Oct 8, 2024Updated last year
- ☆43Mar 10, 2025Updated 11 months ago
- Fix syntax errors of LLM-generated RTL☆43May 23, 2024Updated last year
- ☆44May 18, 2024Updated last year
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆38May 17, 2024Updated last year
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆42May 29, 2025Updated 9 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆144Jul 23, 2025Updated 7 months ago
- ☆23Jan 30, 2025Updated last year
- Automated Repair of Verilog Hardware Descriptions☆36Jan 16, 2025Updated last year
- ☆13Feb 6, 2021Updated 5 years ago
- This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generati…☆21Sep 25, 2025Updated 5 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆99Mar 29, 2024Updated last year
- This repository hosts the information of SPICEPilot: a training free LLM data-augmentation, new bench marking and future road-map.☆30May 23, 2025Updated 9 months ago
- ☆34Dec 21, 2025Updated 2 months ago
- ☆20Jun 12, 2024Updated last year
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Simple Python interface for ABC☆29May 19, 2023Updated 2 years ago
- LLM-Enhanced Bayesian Optimization for Efficient Analog Constraint Generation☆30Oct 28, 2024Updated last year
- This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…☆187Jun 15, 2025Updated 8 months ago
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆33Jun 5, 2024Updated last year
- Open source version of ArchGym project.☆125Apr 13, 2025Updated 10 months ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12May 24, 2019Updated 6 years ago
- A template-based, layer-oriented High Level Synthesis Tool for AI algorithms☆13Dec 15, 2025Updated 2 months ago
- ☆339Jan 13, 2026Updated last month
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Oct 6, 2019Updated 6 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- ☆109Dec 5, 2019Updated 6 years ago
- [NeurIPS 2022 Spotlight] MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning☆68Jan 5, 2026Updated 2 months ago
- DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)☆117May 18, 2023Updated 2 years ago
- ☆99Jun 24, 2025Updated 8 months ago
- Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source☆303Jan 5, 2026Updated 2 months ago
- ☆13Dec 31, 2022Updated 3 years ago
- Digital Standard Cells based SAR ADC☆14Aug 5, 2021Updated 4 years ago