Alternatives and similar repositories for CodeGen-Fine-Tuning

Users that are interested in CodeGen-Fine-Tuning are comparing it to the libraries listed below

• ZixiBenZhang / ml4dv
  LLM4DV
  ☆15Updated 11 months ago
• shailja-thakur / VGen
  ☆179Updated 10 months ago
• NVlabs / RTLFixer
  Fix syntax errors of LLM-generated RTL
  ☆36Updated last year
• LearningOpt / pie
  ☆52Updated last year
• GATECH-EIC / LLM4HWDesign_Starting_Toolkit
  LLM4HWDesign Starting Toolkit
  ☆18Updated 10 months ago
• stable-lab / MAGE
  MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  ☆58Updated 4 months ago
• hammad-a / verilog_repair
  Automated Repair of Verilog Hardware Descriptions
  ☆32Updated 7 months ago
• GATECH-EIC / mg-verilog
  ☆47Updated 10 months ago
• reddy-lab-code-research / XLCoST
  Code and data for XLCoST: A Benchmark Dataset for Cross-lingual Code Intelligence
  ☆80Updated 7 months ago
• AutoBench / AutoBench
  ☆26Updated 4 months ago
• madaan / pie-perf
  Training language models to make programs faster
  ☆92Updated last year
• IPRC-DIP / CodeV
  ☆47Updated 3 months ago
• hkust-zhiyao / RTL-Coder
  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
  ☆223Updated 6 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆130Updated 9 months ago
• reddy-lab-code-research / PPOCoder
  Code for the TMLR 2023 paper "PPOCoder: Execution-based Code Generation using Deep Reinforcement Learning"
  ☆113Updated last year
• NVlabs / verilog-eval
  Verilog evaluation benchmark for large language model
  ☆311Updated last month
• Thinklab-SJTU / Awesome-LLM4EDA
  ☆225Updated last year
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆29Updated 4 months ago
• neulab / code-bert-score
  CodeBERTScore: an automatic metric for code generation, based on BERTScore
  ☆199Updated last year
• hkust-zhiyao / SpecLLM
  SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
  ☆15Updated last year
• HPAI-BSC / TuRTLe
  TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)
  ☆19Updated last month
• achieve-lab / assertion_data_for_LLM
  ☆16Updated 7 months ago
• magicYang1573 / llm-hardware-test-generation
  ☆32Updated last year
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆23Updated 4 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆38Updated 10 months ago
• ACADLab / SPICEPilot
  This repository hosts the information of SPICEPilot: a training free LLM data-augmentation, new bench marking and future road-map.
  ☆21Updated 3 months ago
• gpt4rtl / AutoSVA2
  ☆17Updated last year
• hkust-zhiyao / NetTAG
  NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)
  ☆14Updated 2 weeks ago
• AutoBench / CorrectBench
  ☆24Updated 5 months ago
• Gy-Hu / AIG2INV
  DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)
  ☆11Updated last year