NVlabs / VerilogCoderLinks
☆93Updated 10 months ago
Alternatives and similar repositories for VerilogCoder
Users that are interested in VerilogCoder are comparing it to the libraries listed below
Sorting:
- An open-source benchmark for generating design RTL with natural language☆153Updated last year
- ☆40Updated 10 months ago
- ☆193Updated last year
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆246Updated 11 months ago
- ☆227Updated 9 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆197Updated 5 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆43Updated last year
- Verilog evaluation benchmark for large language model☆361Updated 5 months ago
- ☆183Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- A Fast, Low-Overhead On-chip Network☆257Updated 3 weeks ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆102Updated this week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆96Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆80Updated 9 months ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆153Updated last week
- This is a tutorial on standard digital design flow☆82Updated 4 years ago
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆87Updated last year
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- ☆98Updated this week
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆97Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last week
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆103Updated 6 months ago
- ☆46Updated last year
- [WIP] Dockerize Synopsys/Cadence EDA tools☆95Updated 6 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆62Updated 7 months ago