☆133Mar 10, 2025Updated last year
Alternatives and similar repositories for VerilogCoder
Users that are interested in VerilogCoder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆99Apr 11, 2025Updated last year
- ☆145Mar 11, 2026Updated 3 weeks ago
- Verilog evaluation benchmark for large language model☆399Jul 14, 2025Updated 8 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆35Apr 13, 2025Updated 11 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆41Apr 3, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆16Jan 29, 2024Updated 2 years ago
- ☆39Apr 11, 2025Updated 11 months ago
- ☆28Jun 25, 2024Updated last year
- Project Status: Discontinued, New repository: spec2rtl-plugin☆24Feb 1, 2026Updated 2 months ago
- ☆20Jun 12, 2024Updated last year
- The official implementation of DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model (ICLR 2025)☆16Dec 18, 2025Updated 3 months ago
- ☆275Jul 8, 2024Updated last year
- ☆47Mar 10, 2025Updated last year
- MLIR+EqSat☆26Jan 10, 2026Updated 3 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- [Mlsys'22] Understanding gnn computational graph: A coordinated computation, io, and memory perspective☆22Sep 11, 2023Updated 2 years ago
- ☆45May 18, 2024Updated last year
- ☆40Dec 21, 2025Updated 3 months ago
- Unified Sparse Library Wrapper Based on cuSPARSE☆12May 24, 2022Updated 3 years ago
- ☆19Aug 30, 2020Updated 5 years ago
- This repository contains a comprehensive collection of parameterized and configurable RTL modules written in Verilog, organized by catego…☆18Sep 23, 2025Updated 6 months ago
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆25Jul 24, 2025Updated 8 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆71May 29, 2025Updated 10 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆278Feb 9, 2025Updated last year
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Nov 1, 2022Updated 3 years ago
- Zynq PR Management☆13Apr 20, 2016Updated 9 years ago
- Testbenches for HDL projects☆23Updated this week
- Using e-graphs for logic synthesis (ICCAD'25)☆33Updated this week
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- FPGA for uSDR☆21Mar 27, 2026Updated 2 weeks ago
- The source code for the XTRX FPGA image☆17Nov 19, 2022Updated 3 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- [ICML 2023] ChiPFormer: Transferable Chip Placement via Offline Decision Transformer☆54Feb 22, 2026Updated last month
- LLM4DV☆18Sep 30, 2024Updated last year
- LLM Agent for Hardware Description Language☆21Jun 7, 2025Updated 10 months ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆11May 24, 2019Updated 6 years ago
- DeepGate3 for ICCAD2024☆14May 26, 2025Updated 10 months ago
- Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.☆19Feb 9, 2022Updated 4 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆35Dec 25, 2025Updated 3 months ago