Alternatives and similar repositories for VerilogCoder

Users that are interested in VerilogCoder are comparing it to the libraries listed below

• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆180Updated 5 years ago
• The-OpenROAD-Project / asap7
  ☆175Updated 4 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆121Updated 8 months ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆78Updated 4 years ago
• ncsu-eda / FreePDK3
  ☆150Updated 3 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 2 years ago
• shailja-thakur / AutoChip
  ☆30Updated 4 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆257Updated 4 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆52Updated last month
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆72Updated 4 years ago
• hkust-zhiyao / RTL-Coder
  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
  ☆210Updated 5 months ago
• NVlabs / INSTA
  ☆77Updated 3 weeks ago
• parallaxsw / OpenSTA
  ☆76Updated this week
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆85Updated last month
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆34Updated last year
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆94Updated last year
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆83Updated last year
• magical-eda / OpenSAR
  ☆15Updated 3 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆59Updated last year
• NVlabs / verilog-eval
  Verilog evaluation benchmark for large language model
  ☆288Updated 5 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆120Updated this week
• ABKGroup / PROBE3.0
  ☆44Updated last year
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆92Updated 2 weeks ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated last month
• shailja-thakur / VGen
  ☆171Updated 9 months ago
• vaughnbetz / COFFE
  ☆43Updated 10 months ago
• NVlabs / CircuitOps
  ☆86Updated 3 weeks ago
• EECS150 / asic_labs_sp22
  ☆23Updated 2 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 4 years ago