NVlabs / VerilogCoderLinks
☆68Updated 7 months ago
Alternatives and similar repositories for VerilogCoder
Users that are interested in VerilogCoder are comparing it to the libraries listed below
Sorting:
- An open-source benchmark for generating design RTL with natural language☆134Updated 11 months ago
- ☆197Updated 7 months ago
- ☆37Updated 7 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆187Updated 5 years ago
- Verilog evaluation benchmark for large language model☆323Updated 2 months ago
- ☆184Updated 11 months ago
- A Fast, Low-Overhead On-chip Network☆228Updated last week
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆92Updated this week
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆227Updated 8 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆82Updated last year
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆64Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆57Updated 4 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆268Updated last week
- ☆106Updated 5 years ago
- Logic synthesis and ABC based optimization☆50Updated this week
- An AXI4 crossbar implementation in SystemVerilog☆175Updated last month
- ☆176Updated 4 years ago
- Introductory course into static timing analysis (STA).☆97Updated 3 months ago
- ☆44Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆65Updated 6 months ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 10 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆78Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- ☆88Updated 3 months ago
- Modular Multi-ported SRAM-based Memory☆31Updated 11 months ago