A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
☆11May 24, 2019Updated 7 years ago
Alternatives and similar repositories for ride-core-demo
Users that are interested in ride-core-demo are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆15Feb 6, 2021Updated 5 years ago
- ☆33Nov 2, 2025Updated 7 months ago
- ☆21Jun 12, 2024Updated 2 years ago
- ☆24Feb 11, 2021Updated 5 years ago
- Automatic generation of architecture-level models for hardware from its RTL design.☆16Apr 12, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- RISC-V Formal in Chisel☆13Apr 9, 2024Updated 2 years ago
- Pono: A flexible and extensible SMT-based model checker☆125Jun 4, 2026Updated 2 weeks ago
- ILA Model Database☆24Sep 27, 2020Updated 5 years ago
- 32-bit RISC-V Emulator☆27Feb 23, 2019Updated 7 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Equivalence checking with Yosys☆60Jun 4, 2026Updated 2 weeks ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆30Dec 23, 2025Updated 5 months ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14May 7, 2022Updated 4 years ago
- A generic C++ API for SMT solving. It provides abstract classes which can be implemented by different SMT solvers.☆141Apr 16, 2026Updated 2 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A Modeling and Verification Platform for SoCs using ILAs☆82Jul 3, 2024Updated last year
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Post-Silicon Validation Tool based on REVERSI☆11Dec 10, 2025Updated 6 months ago
- Recent papers related to hardware formal verification.☆77Sep 20, 2023Updated 2 years ago
- FPGA-based HyperLogLog Accelerator☆12Jul 13, 2020Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆102Mar 29, 2024Updated 2 years ago
- GeST (Generating Stress-Tests) is a Genetic Algorithm framework for automatic hardware stress-test generation. Related scientific publica…☆15May 7, 2019Updated 7 years ago
- Reads a state transition system and performs property checking☆93Sep 12, 2025Updated 9 months ago
- ☆14Jan 3, 2018Updated 8 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Lean 4 library of tools for parsing and compiling syntax and parser definitions.☆16Dec 10, 2023Updated 2 years ago
- A high-performance hardware accelerator for compression/decompression algorithm library of zlib based on kunpeng processor☆17May 19, 2021Updated 5 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆110Updated this week
- ☆15Sep 14, 2020Updated 5 years ago
- A verified Implementation of a mini prolog☆17Nov 27, 2022Updated 3 years ago
- A RISC-V RV32 model ready for SMT program synthesis.☆12Jun 23, 2021Updated 4 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 7 months ago
- ☆13Jan 20, 2023Updated 3 years ago
- Code for the paper "LLM Meets Bounded Model Checking: Neuro-symbolic Loop Invariant Inference" at ASE 2024☆30Sep 3, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A RISC-V CPU implementation☆17Apr 9, 2020Updated 6 years ago
- ☆20Dec 3, 2019Updated 6 years ago
- ☆18Jul 12, 2024Updated last year
- A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer☆18Dec 11, 2018Updated 7 years ago
- Implementation of the IC3 / Property Directed Reachability algorithm using the the Z3 SMT solver.☆18Apr 30, 2016Updated 10 years ago
- RTLCheck☆25Oct 9, 2018Updated 7 years ago
- ☆14Jun 28, 2018Updated 7 years ago