Alternatives and similar repositories for mg-verilog:

Users that are interested in mg-verilog are comparing it to the libraries listed below

• mit-han-lab / spatten
  [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
  ☆84Updated 7 months ago
• mec-UMN / HISIM
  HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…
  ☆35Updated last month
• abdelfattah-lab / BitMoD-HPCA-25
  ☆29Updated 4 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆103Updated 5 months ago
• pku-liang / OriGen
  OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)
  ☆18Updated 6 months ago
• UIUC-ChenLab / Chrysalis-HLS
  ☆12Updated 7 months ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆50Updated last month
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆39Updated 4 months ago
• stable-lab / MAGE
  MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  ☆41Updated 2 weeks ago
• UCLA-DM / HLSyn
  HLSyn benchmark for paper "Towards a Comprehensive Benchmark for FPGA Targeted High-Level Synthesis"
  ☆29Updated last year
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆24Updated last year
• mit-emze / cimloop
  ☆56Updated 3 weeks ago
• IPRC-DIP / CodeV
  ☆23Updated this week
• hkust-zhiyao / PANDA
  PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
  ☆15Updated last year
• hkust-zhiyao / RTL-Coder
  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
  ☆183Updated 2 months ago
• hatsu3 / Sanger
  ☆43Updated 3 years ago
• magicYang1573 / llm-hardware-test-generation
  ☆27Updated 9 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆74Updated 3 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆26Updated 8 months ago
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆71Updated 2 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆78Updated 8 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 6 months ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆31Updated this week
• shailja-thakur / VGen
  ☆145Updated 6 months ago
• GATECH-EIC / ViTCoD
  [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design
  ☆105Updated last year
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆52Updated 3 years ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆23Updated last year
• Zhaoshixin-sky / CIM-MLC
  [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators
  ☆30Updated 11 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆45Updated 7 months ago
• kachris / survey_HA_LLM
  A survey on Hardware Accelerated LLMs
  ☆50Updated 3 months ago