GATECH-EIC / mg-verilogLinks
☆49Updated last year
Alternatives and similar repositories for mg-verilog
Users that are interested in mg-verilog are comparing it to the libraries listed below
Sorting:
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆67Updated 6 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆232Updated 8 months ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆112Updated last year
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆50Updated 10 months ago
- An open-source benchmark for generating design RTL with natural language☆135Updated 11 months ago
- ☆14Updated last year
- ☆184Updated last year
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆51Updated 7 months ago
- Verilog evaluation benchmark for large language model☆331Updated 3 months ago
- ☆68Updated 3 weeks ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆72Updated 6 months ago
- ☆31Updated last year
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆26Updated last year
- ☆49Updated last month
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆122Updated 2 years ago
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆44Updated 3 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆32Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆87Updated last year
- ☆13Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆33Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆81Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆68Updated last month
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆17Updated 2 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆58Updated 2 weeks ago
- ☆60Updated 7 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆71Updated last year
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆97Updated 6 months ago
- ACM TODAES Best Paper Award, 2022☆30Updated 2 years ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆16Updated last year