DfX-NYUAD / LLM4IC
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
☆15Updated 5 months ago
Related projects ⓘ
Alternatives and complementary repositories for LLM4IC
- ☆127Updated 4 months ago
- An open-source benchmark for generating design RTL with natural language☆68Updated this week
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆35Updated last month
- This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…☆127Updated 4 months ago
- Verilog evaluation benchmark for large language model☆175Updated 2 months ago
- ☆117Updated 3 weeks ago
- ☆9Updated 2 months ago
- ☆44Updated last month
- ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms☆18Updated last month
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability. This collection of paper…☆39Updated last year
- ☆21Updated 4 months ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆17Updated 4 months ago
- ☆20Updated last month
- ☆71Updated 3 weeks ago
- ☆19Updated this week
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆127Updated 3 weeks ago
- Dataset for ML-guided Accelerator Design☆31Updated 7 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆20Updated last week
- ☆28Updated 2 years ago
- awesome-Analog-IC-Design-Automation☆29Updated last year
- VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…☆24Updated 2 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆75Updated last week
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA☆16Updated 3 months ago
- LLM-Enhanced Bayesian Optimization for Efficient Analog Constraint Generation☆10Updated last week
- ☆29Updated last year
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆115Updated last month
- ☆13Updated 2 weeks ago
- Collection of digital hardware modules & projects (benchmarks)☆31Updated last week
- ☆27Updated 11 months ago
- This is a repo to store circuit design datasets☆15Updated 9 months ago