Alternatives and similar repositories for LLM4IC

Users that are interested in LLM4IC are comparing it to the libraries listed below

• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆42Updated 6 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆112Updated 7 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆50Updated 3 weeks ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆31Updated 7 months ago
• UIUC-ChenLab / Chrysalis-HLS
  ☆14Updated 9 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆52Updated 3 weeks ago
• AutoBench / AutoBench
  ☆24Updated 2 months ago
• Picrew / EDA_LLM
  Papers on LLM4EDA from 2023 and 2024
  ☆34Updated 11 months ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆17Updated 2 months ago
• magicYang1573 / llm-hardware-test-generation
  ☆31Updated 11 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated last year
• NVlabs / CircuitOps
  ☆81Updated 2 months ago
• OpenROAD-Assistant / EDA-Corpus
  Datasets for EDA LLM research
  ☆29Updated 5 months ago
• shailja-thakur / VGen
  ☆155Updated 8 months ago
• Thinklab-SJTU / Awesome-LLM4EDA
  ☆204Updated 11 months ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• Entropy-xcy / sns
  ☆18Updated 2 years ago
• GATECH-EIC / mg-verilog
  ☆46Updated 8 months ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆45Updated last week
• bu-icsg / TAP-2.5D
  ☆33Updated 4 years ago
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆13Updated 8 months ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆30Updated 2 weeks ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆18Updated last month
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆50Updated 5 months ago
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆52Updated last month
• vaughnbetz / COFFE
  ☆42Updated 9 months ago
• laiyao1 / AnalogCoder
  ☆61Updated 3 months ago
• zshi0616 / python-deepgate
  ☆22Updated last year
• aichipdesign / chipgptv
  Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
  ☆23Updated last week
• CODA-Team / AnalogGym
  ☆48Updated 3 weeks ago