LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
☆38May 17, 2024Updated last year
Alternatives and similar repositories for LLM4IC
Users that are interested in LLM4IC are comparing it to the libraries listed below
Sorting:
- ☆16Aug 29, 2024Updated last year
- Papers on LLM4EDA from 2023 and 2024☆46Jul 6, 2024Updated last year
- ☆265Jul 8, 2024Updated last year
- LEC - Logic Equivalence Checking - Formal Verification☆33Updated this week
- ☆14Sep 3, 2024Updated last year
- ☆10Oct 15, 2021Updated 4 years ago
- ☆201Oct 17, 2024Updated last year
- Fix syntax errors of LLM-generated RTL☆43May 23, 2024Updated last year
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS☆15Feb 27, 2021Updated 5 years ago
- [NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs☆15Feb 22, 2026Updated last week
- RISC-V ISA based 32-bit processor written in HLS☆16Nov 7, 2019Updated 6 years ago
- ☆23Jan 30, 2025Updated last year
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆21Mar 20, 2025Updated 11 months ago
- ☆19Jul 12, 2024Updated last year
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆34Feb 11, 2026Updated 3 weeks ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆49Feb 24, 2026Updated last week
- DNN Compiler for Heterogeneous SoCs☆62Updated this week
- An open-source benchmark for generating design RTL with natural language☆162Nov 8, 2024Updated last year
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- Collection of kernel accelerators optimised for LLM execution☆27Feb 26, 2026Updated last week
- A Language for Closed-form High-level ARchitecture Modeling☆21Feb 10, 2020Updated 6 years ago
- Code repository for Coppelia tool☆23Nov 12, 2020Updated 5 years ago
- libView is a GUI tool for library file cell information view and comparison.☆26Jul 24, 2023Updated 2 years ago
- Corblivar is a simulated-annealing-based floorplanning suite for 3D ICs☆34Jun 1, 2024Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆73Sep 29, 2025Updated 5 months ago
- ☆24Jun 3, 2024Updated last year
- Simple UVM environment for experimenting with Verilator.☆37Updated this week
- An advanced circuit-based sat solver☆36Feb 24, 2025Updated last year
- LLM-Enhanced Bayesian Optimization for Efficient Analog Constraint Generation☆30Oct 28, 2024Updated last year
- A Modular Open-Source Hardware Fuzzing Framework☆36Dec 14, 2021Updated 4 years ago
- Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"☆27Dec 9, 2018Updated 7 years ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆37Jun 17, 2025Updated 8 months ago
- A design automation framework to engineer decision diagrams yourself☆25Updated this week
- ☆29Oct 4, 2017Updated 8 years ago
- This is the code for our paper "Reinforcement Learning within Tree Search for Fast Macro Placement".☆34Nov 13, 2024Updated last year
- ☆33Jul 1, 2024Updated last year
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆35Apr 15, 2020Updated 5 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated last year