AUCOHL / RTL-RepoLinks
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24
☆14Updated last year
Alternatives and similar repositories for RTL-Repo
Users that are interested in RTL-Repo are comparing it to the libraries listed below
Sorting:
- An open-source benchmark for generating design RTL with natural language☆112Updated 7 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆31Updated 8 months ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆23Updated last week
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆42Updated 6 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆50Updated 3 weeks ago
- ☆43Updated 3 weeks ago
- Fast Symbolic Repair of Hardware Design Code☆24Updated 5 months ago
- ☆155Updated 8 months ago
- ☆28Updated 3 months ago
- ☆39Updated 2 years ago
- ☆24Updated 2 months ago
- ☆59Updated last week
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆17Updated 2 months ago
- ☆52Updated 3 weeks ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆205Updated 4 months ago
- ☆31Updated 11 months ago
- ☆14Updated 9 months ago
- A toolchain for rapid design space exploration of chiplet architectures☆52Updated last month
- ☆15Updated 4 years ago
- Source files to reproduce the results shown for A-QED at DAC 2020☆8Updated 4 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆35Updated 4 months ago
- SRAM☆22Updated 4 years ago
- ☆22Updated 2 months ago
- Open source process design kit for 28nm open process☆59Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- This is a python repo for flattening Verilog☆18Updated last month
- An infrastructure for integrated EDA☆41Updated last year
- ☆25Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆46Updated 2 months ago
- ☆27Updated 7 years ago