Alternatives and similar repositories for verilog_repair

Users that are interested in verilog_repair are comparing it to the libraries listed below

• gpt4rtl / AutoSVA2
  ☆17Updated last year
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆30Updated 6 months ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆67Updated 3 weeks ago
• achieve-lab / assertion_data_for_LLM
  ☆18Updated 8 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆38Updated 11 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆26Updated 8 months ago
• NVlabs / RTLFixer
  Fix syntax errors of LLM-generated RTL
  ☆37Updated last year
• efeslab / asplos22-hardware-debugging-artifact
  ☆13Updated last year
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆10Updated 11 months ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆16Updated 6 years ago
• hkustgz-zhang-lab / HW-Formal-Paper
  Recent papers related to hardware formal verification.
  ☆73Updated 2 years ago
• ekiwi / simulator-independent-coverage
  Project Repo for the Simulator Independent Coverage Research
  ☆21Updated 2 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆77Updated last year
• ekiwi / rfuzz
  rfuzz: coverage-directed fuzzing for RTL research platform
  ☆111Updated 3 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆34Updated 3 years ago
• HWSec-UNC / Sylvia
  ☆18Updated 3 months ago
• efeslab / hardware-bugbase
  ☆19Updated last year
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• zilongwang123 / LeaVe
  A tool for checking the contract satisfaction for hardware designs
  ☆11Updated 2 weeks ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆42Updated 2 weeks ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• Entropy-xcy / sns
  ☆19Updated 2 years ago
• Moorvan / RISCV-Formal-Chisel
  RISC-V Formal in Chisel
  ☆11Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 4 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 3 years ago
• AutoBench / CorrectBench
  ☆23Updated 6 months ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆83Updated last week
• yaoxufeng / RTLRewriter-Bench
  ☆38Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆19Updated 4 months ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆23Updated 5 years ago