Automated Repair of Verilog Hardware Descriptions
☆36Jan 16, 2025Updated last year
Alternatives and similar repositories for verilog_repair
Users that are interested in verilog_repair are comparing it to the libraries listed below
Sorting:
- ☆17Nov 19, 2023Updated 2 years ago
- ☆13Jun 12, 2024Updated last year
- ☆13Feb 6, 2021Updated 5 years ago
- Fast Symbolic Repair of Hardware Design Code☆33Jan 20, 2025Updated last year
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- ☆18Jul 11, 2021Updated 4 years ago
- ☆11Mar 8, 2021Updated 4 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- ☆14Sep 14, 2020Updated 5 years ago
- Fuzz everything! Now let's fuzz chip!☆35Feb 11, 2026Updated 3 weeks ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆50Oct 28, 2024Updated last year
- ☆15May 24, 2023Updated 2 years ago
- Using GNN and DQN to find a baetter branching heuristic for a CDCL Solver☆53Oct 20, 2020Updated 5 years ago
- ☆15Nov 9, 2022Updated 3 years ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Nov 8, 2016Updated 9 years ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- ☆20Jun 12, 2024Updated last year
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Sep 4, 2025Updated 6 months ago
- Fix syntax errors of LLM-generated RTL☆43May 23, 2024Updated last year
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 6 years ago
- ☆19Jul 12, 2024Updated last year
- ☆19Dec 21, 2020Updated 5 years ago
- ☆20Oct 27, 2022Updated 3 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆103Updated this week
- ☆25Mar 1, 2023Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆99Mar 29, 2024Updated last year
- ☆26Nov 2, 2025Updated 4 months ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- Integer Multiplier Generator for Verilog☆24Jul 4, 2025Updated 8 months ago
- IC3 reference implementation: a short, simple, fairly competitive implementation of IC3. Read it, tune it, extend it, play with it.☆64May 31, 2015Updated 10 years ago
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 7 months ago
- NeuroCore: Guiding CDCL with Unsat-Core Predictions☆47Feb 17, 2020Updated 6 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- ☆20Feb 28, 2026Updated last week
- work in progress, playing around with btor2 in rust☆12Feb 24, 2026Updated last week
- This repository includes the data and scripts utilized in the study titled "Improving LLM-based Verilog Code Generation with Data Augment…☆13Mar 24, 2025Updated 11 months ago