Automated Repair of Verilog Hardware Descriptions
☆37Jan 16, 2025Updated last year
Alternatives and similar repositories for verilog_repair
Users that are interested in verilog_repair are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Fast Symbolic Repair of Hardware Design Code☆34Jan 20, 2025Updated last year
- ☆13Jun 12, 2024Updated last year
- ☆17Nov 19, 2023Updated 2 years ago
- ☆13Feb 6, 2021Updated 5 years ago
- Fuzz everything! Now let's fuzz chip!☆35Feb 11, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- ☆18Jul 11, 2021Updated 4 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆57Oct 28, 2024Updated last year
- ☆11Mar 8, 2021Updated 5 years ago
- ☆20Jun 12, 2024Updated last year
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆37Dec 14, 2021Updated 4 years ago
- Using GNN and DQN to find a baetter branching heuristic for a CDCL Solver☆54Oct 20, 2020Updated 5 years ago
- Fix syntax errors of LLM-generated RTL☆45May 23, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- ☆26Nov 2, 2025Updated 4 months ago
- ☆25Mar 1, 2023Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆99Mar 29, 2024Updated last year
- A SystemVerilog Assertion dataset to improve hardware verification with LLMs.☆23Jun 9, 2025Updated 9 months ago
- Hack@DAC 2021☆18Jul 24, 2024Updated last year
- ☆14Sep 14, 2020Updated 5 years ago
- ☆13Feb 14, 2026Updated last month
- ☆20Oct 27, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆11May 24, 2019Updated 6 years ago
- A tool of collecting patch-related commits and parsing patches.☆13Dec 2, 2018Updated 7 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆102Updated this week
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 4 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 6 months ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Sep 4, 2025Updated 6 months ago
- ☆15May 24, 2023Updated 2 years ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Nov 8, 2016Updated 9 years ago
- Papers on LLM4EDA from 2023 and 2024☆47Jul 6, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆18Nov 9, 2022Updated 3 years ago
- Generative Benchmark for LLM-Aided Hardware Design☆27Jun 4, 2025Updated 9 months ago
- ☆18Jul 12, 2024Updated last year
- ☆22Mar 12, 2026Updated 2 weeks ago
- AIGER And-Inverter-Graph Library☆98Feb 17, 2026Updated last month
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- ☆45Mar 2, 2023Updated 3 years ago