This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
☆29Sep 25, 2025Updated 11 months ago
Alternatives and similar repositories for VeriReason
Users that are interested in VeriReason are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆44Jul 9, 2025Updated last year
- ☆57Jan 6, 2026Updated 7 months ago
- This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis O…☆108Jul 29, 2025Updated last year
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆34Jun 5, 2024Updated 2 years ago
- LLM4HWDesign Starting Toolkit☆20Oct 4, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆65Sep 4, 2025Updated 11 months ago
- PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification☆36Dec 11, 2025Updated 8 months ago
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆34Oct 20, 2024Updated last year
- HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Levels Synthesis Design Tasks☆21Updated this week
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆321Feb 9, 2025Updated last year
- ICRTL Benchmark: Industrial-level RTL design challenges for evaluating PPA optimization, code generation, and LLM applications in EDA.☆31Jul 3, 2026Updated last month
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025, ACM TODAES 2026)☆48Jul 22, 2026Updated last month
- Datasets for EDA LLM research☆46Jan 17, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆35May 4, 2025Updated last year
- ☆44Apr 11, 2025Updated last year
- ICCD'24 paper: "AutoVCoder: A systematic framework for automated verilog code generation"☆26Dec 17, 2024Updated last year
- Fix syntax errors of LLM-generated RTL☆57May 23, 2024Updated 2 years ago
- ☆61Mar 10, 2025Updated last year
- Verilog evaluation benchmark for large language model☆466Jul 14, 2025Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆135Apr 11, 2025Updated last year
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆49May 29, 2025Updated last year
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆61Dec 17, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆40Jun 17, 2025Updated last year
- An open-source benchmark for generating design RTL with natural language☆223Aug 15, 2026Updated 2 weeks ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆58May 21, 2025Updated last year
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆32Jul 24, 2025Updated last year
- The first large scale formally verified reasoning dataset for Verilog☆24May 16, 2025Updated last year
- LLM4DV☆23Sep 30, 2024Updated last year
- ☆18Feb 25, 2026Updated 6 months ago
- Generative Benchmark for LLM-Aided Hardware Design☆30Jun 4, 2025Updated last year
- Correlation Power Analysis☆13Aug 3, 2018Updated 8 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆20Jan 17, 2026Updated 7 months ago
- ☆16May 3, 2024Updated 2 years ago
- Project Status: Discontinued, New repository: spec2rtl-plugin☆31Feb 1, 2026Updated 7 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆44Apr 3, 2025Updated last year
- A retargetable and extensible synthesis-based compiler for modern hardware architectures☆20Nov 20, 2025Updated 9 months ago
- Code for paper 'ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection'☆15Jul 4, 2025Updated last year
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆43Apr 13, 2025Updated last year