Alternatives and similar repositories for pyhdl-eval

Users that are interested in pyhdl-eval are comparing it to the libraries listed below

• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 5 years ago
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆37Updated last year
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆48Updated 4 months ago
• gvsoc / gvsoc
  ☆23Updated this week
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆29Updated last year
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated last month
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆38Updated this week
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆53Updated 2 months ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆37Updated 3 weeks ago
• wincle626 / HLS_Legup
  ☆27Updated 7 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆48Updated 3 weeks ago
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆43Updated 7 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆59Updated last year
• pulp-platform / ELAU
  ☆19Updated last year
• StanfordAHA / CGRAFlow
  Integration test for entire CGRA flow
  ☆12Updated 5 years ago
• VeriGOOD-ML / public
  ☆60Updated 2 months ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 3 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆31Updated last year
• pku-dasys / cocoon
  An infrastructure for integrated EDA
  ☆41Updated last year
• jasonlin316 / Systolic-Array-for-Smith-Waterman
  This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …
  ☆26Updated 6 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 7 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• OpenROAD-Assistant / EDA-Corpus
  Datasets for EDA LLM research
  ☆30Updated 6 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆41Updated last month
• pulp-platform / redmule
  ☆68Updated this week
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆112Updated last year
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 4 years ago