Alternatives and similar repositories for EDA_LLM

Users that are interested in EDA_LLM are comparing it to the libraries listed below

• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆150Updated last year
• Thinklab-SJTU / Awesome-LLM4EDA
  ☆257Updated last year
• hkust-zhiyao / RTL-Coder
  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
  ☆243Updated 10 months ago
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆55Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆59Updated 6 months ago
• shailja-thakur / VGen
  ☆193Updated last year
• ChatDesignVerification / GenBen
  Generative Benchmark for LLM-Aided Hardware Design
  ☆24Updated 6 months ago
• NVlabs / verilog-eval
  Verilog evaluation benchmark for large language model
  ☆355Updated 5 months ago
• DfX-NYUAD / LLM4IC
  LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
  ☆34Updated last year
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆75Updated 6 months ago
• bu-icsg / TAP-2.5D
  ☆39Updated 4 years ago
• charley871103 / TPU
  AI Chip project
  ☆33Updated 4 years ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆44Updated last year
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆103Updated 5 months ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆144Updated 7 months ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆166Updated 8 months ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆59Updated 6 months ago
• dldldlfma / super_small_toy_tpu
  ☆45Updated 4 years ago
• The-OpenROAD-Project / asap7
  ☆218Updated 9 months ago
• skycrapers / AM-Lib
  ☆30Updated 2 years ago
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆140Updated 10 months ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆45Updated 6 months ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆30Updated 2 years ago
• BUAA-CI-LAB / Literatures-on-SRAM-based-CIM
  A reading list for SRAM-based Compute-In-Memory (CIM) research.
  ☆108Updated last month
• Linger0 / SRAM-Compute-In-Memory
  A collection of research papers on SRAM-based compute-in-memory architectures.
  ☆30Updated 2 years ago
• hkust-zhiyao / PANDA
  PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
  ☆17Updated 2 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 9 months ago
• vaughnbetz / COFFE
  ☆46Updated last year
• aichipdesign / chipgptv
  Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
  ☆30Updated 6 months ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆109Updated 11 months ago