lukasc-ch / ExtendedBitPlaneCompressionLinks
Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Lukas Cavigelli, Georg Rutishauser, Luca Benini.
☆20Updated 6 years ago
Alternatives and similar repositories for ExtendedBitPlaneCompression
Users that are interested in ExtendedBitPlaneCompression are comparing it to the libraries listed below
Sorting:
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- ☆71Updated 5 years ago
- ☆72Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- A DAG processor and compiler for a tree-based spatial datapath.☆14Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆57Updated 5 months ago
- Eyeriss chip simulator☆36Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- ☆23Updated 3 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆141Updated 5 years ago
- ☆60Updated 5 years ago
- ☆10Updated 10 months ago
- ☆35Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆16Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 3 months ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- ☆23Updated 3 years ago
- ☆30Updated 6 months ago
- ☆35Updated 5 years ago
- ☆37Updated 6 months ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆53Updated last year
- ☆36Updated 4 years ago
- Adaptive floating-point based numerical format for resilient deep learning☆14Updated 3 years ago
- NeuraLUT-Assemble☆41Updated last month