NVlabs / RTLFixerLinks
Fix syntax errors of LLM-generated RTL
☆30Updated last year
Alternatives and similar repositories for RTLFixer
Users that are interested in RTLFixer are comparing it to the libraries listed below
Sorting:
- ☆27Updated this week
- ☆45Updated 7 months ago
- ☆52Updated last week
- ☆30Updated 11 months ago
- An open-source benchmark for generating design RTL with natural language☆111Updated 6 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆13Updated last month
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆27Updated last year
- LLM4HWDesign Starting Toolkit☆17Updated 8 months ago
- ☆11Updated 10 months ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆23Updated 10 months ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆41Updated 5 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆200Updated 3 months ago
- ☆25Updated last month
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆30Updated 7 months ago
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆19Updated 7 months ago
- This is a python repo for flattening Verilog☆17Updated 3 weeks ago
- ☆153Updated 7 months ago
- HLSyn benchmark for paper "Towards a Comprehensive Benchmark for FPGA Targeted High-Level Synthesis"☆29Updated last year
- VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…☆26Updated 2 years ago
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆13Updated last year
- ☆17Updated 2 years ago
- ☆198Updated 10 months ago
- ACM TODAES Best Paper Award, 2022☆25Updated last year
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆13Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆45Updated last month
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆48Updated last week
- ☆21Updated 2 years ago
- ☆15Updated last year
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA☆25Updated 2 weeks ago