Fix syntax errors of LLM-generated RTL
☆57May 23, 2024Updated 2 years ago
Alternatives and similar repositories for RTLFixer
Users that are interested in RTLFixer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆44Jul 9, 2025Updated last year
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆35Oct 20, 2024Updated last year
- ☆16May 6, 2026Updated 5 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆45Apr 3, 2025Updated last year
- ☆21Oct 17, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- An open-source benchmark for generating design RTL with natural language☆237Aug 15, 2026Updated last month
- ☆30Aug 18, 2025Updated last year
- Papers on LLM4EDA from 2023 and 2024☆47Jul 6, 2024Updated 2 years ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆325Feb 9, 2025Updated last year
- ☆64Mar 10, 2025Updated last year
- ICCD'24 paper: "AutoVCoder: A systematic framework for automated verilog code generation"☆27Dec 17, 2024Updated last year
- Verilog evaluation benchmark for large language model☆481Jul 14, 2025Updated last year
- ☆188Mar 10, 2025Updated last year
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs