Alternatives and similar repositories for AutoChip:

Users that are interested in AutoChip are comparing it to the libraries listed below

• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆30Updated last year
• aolofsson / POSH
  ☆40Updated 5 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆29Updated last year
• pulp-platform / svase
  ☆31Updated last month
• rahulk29 / sram22
  A configurable SRAM generator
  ☆42Updated last month
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆75Updated 10 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆74Updated this week
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated 3 months ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 3 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆50Updated this week
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆86Updated 3 months ago
• VeriGOOD-ML / public
  ☆53Updated last year
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆25Updated 9 months ago
• aolofsson / IDEA
  ☆32Updated 5 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆21Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆33Updated this week
• black-parrot / black-parrot-sim
  ☆12Updated 2 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆50Updated 3 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated 9 months ago
• yash-k99 / vsdsram
  Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
  ☆19Updated 4 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆35Updated 2 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆25Updated 4 months ago
• pulp-platform / ELAU
  ☆13Updated 7 months ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆17Updated last year
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆22Updated last month
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆51Updated this week