☆43Mar 10, 2025Updated last year
Alternatives and similar repositories for AutoChip
Users that are interested in AutoChip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Project Status: Discontinued, New repository: spec2rtl-plugin☆24Feb 1, 2026Updated last month
- ☆31Jul 12, 2025Updated 8 months ago
- An open-source benchmark for generating design RTL with natural language☆174Nov 8, 2024Updated last year
- LLM4HWDesign Starting Toolkit☆19Oct 4, 2024Updated last year
- ☆29Aug 4, 2025Updated 7 months ago
- ☆199Oct 17, 2024Updated last year
- Firmware for the CTS-SAT-1 ("FrontierSat") mission. Runs on the STM32-based Onboard Computer.☆15Updated this week
- This is an attempt to fine tune SOTA Large Language Models so as to generate Verilog (VHDL) programmes, detect syntax, logic and human er…☆18Mar 12, 2026Updated last week
- ☆23Oct 7, 2025Updated 5 months ago
- ☆33Dec 16, 2021Updated 4 years ago
- ☆55Oct 8, 2024Updated last year
- A dockerized, CPU-only, self-contained version of AUTOMATIC1111's Stable Diffusion Web UI. Unlike other docker images out there, this one…☆19Oct 4, 2022Updated 3 years ago
- ☆31Apr 23, 2024Updated last year
- Code and data release for FEABench: Evaluating Language Models on Multiphysics Reasoning Ability. [MATH-AI workshop, NeurIPS 2024]☆13May 7, 2025Updated 10 months ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆48May 21, 2025Updated 10 months ago
- Project Repo for the Simulator Independent Coverage Research☆21Feb 28, 2023Updated 3 years ago
- ☆126Mar 10, 2025Updated last year
- Hardware of Jasper's Electronic Load R3☆28Sep 26, 2018Updated 7 years ago
- ☆45May 18, 2024Updated last year
- Datasets for EDA LLM research☆39Jan 17, 2025Updated last year
- Use CUDA for eBeam Lithography Simulation☆18Dec 13, 2019Updated 6 years ago
- Verilog evaluation benchmark for large language model☆391Jul 14, 2025Updated 8 months ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Sep 8, 2020Updated 5 years ago
- ☆16Dec 2, 2022Updated 3 years ago
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆15Sep 12, 2022Updated 3 years ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆91Apr 11, 2025Updated 11 months ago
- This repository hosts the information of SPICEPilot: a training free LLM data-augmentation, new bench marking and future road-map.☆32May 23, 2025Updated 10 months ago
- LLM Agent for Hardware Description Language☆21Jun 7, 2025Updated 9 months ago
- 通用IO测试工程，用于捡垃圾测试IO。与BSDL需要对引脚输入不同，该工程只需要确定时钟输入，然后自动向每个IO发送指定字符串，因此只需要将串口接入任意IO查看输出即可☆17Jul 17, 2025Updated 8 months ago
- Combination of Analog Circuit Sizing and DL.☆18Mar 24, 2023Updated 3 years ago
- sketches for egg: a flexible, high-performance e-graph library☆30Sep 25, 2025Updated 6 months ago
- ☆14Mar 13, 2026Updated last week
- Gephi tutorials for data visualisation lecture. A Network Tour of Data Science 2019 Fall semester☆12Apr 11, 2021Updated 4 years ago
- Automated Repair of Verilog Hardware Descriptions☆37Jan 16, 2025Updated last year
- 💡 write type-safe and elegant CLIs with a clear separation of concerns.☆41May 9, 2025Updated 10 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆27Jun 18, 2020Updated 5 years ago
- MICRO 2023 Evaluation Artifact for TeAAL☆10Oct 26, 2023Updated 2 years ago
- A library to parse BLIF (Berkeley Logic Interchange Format) files.☆10Mar 11, 2015Updated 11 years ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆16Apr 7, 2023Updated 2 years ago