shailja-thakur / AutoChipLinks
☆35Updated 6 months ago
Alternatives and similar repositories for AutoChip
Users that are interested in AutoChip are comparing it to the libraries listed below
Sorting:
- ☆183Updated 11 months ago
- An open-source benchmark for generating design RTL with natural language☆130Updated 10 months ago
- ☆62Updated 6 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆225Updated 7 months ago
- SRAM☆23Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- Project repo for the POSH on-chip network generator☆50Updated 6 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 3 months ago
- Collection of digital hardware modules & projects (benchmarks)☆61Updated last week
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆38Updated 10 months ago
- ☆63Updated 4 months ago
- ☆34Updated 2 years ago
- Python wrapper for verilator model☆88Updated last year
- ☆28Updated 5 months ago
- ☆30Updated 3 weeks ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆54Updated 3 months ago
- ☆24Updated last year
- LLM Agent for Hardware Description Language☆19Updated 3 months ago
- Open source process design kit for 28nm open process☆61Updated last year
- This is a python repo for flattening Verilog☆19Updated 4 months ago
- sram/rram/mram.. compiler☆42Updated 2 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆84Updated 4 months ago
- An infrastructure for integrated EDA☆41Updated 2 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆59Updated last month
- ☆105Updated 5 years ago
- ☆45Updated last year
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆90Updated 8 months ago