shailja-thakur / AutoChip
☆26Updated 3 weeks ago
Alternatives and similar repositories for AutoChip:
Users that are interested in AutoChip are comparing it to the libraries listed below
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆44Updated 6 months ago
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆13Updated 9 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆26Updated 5 months ago
- sram/rram/mram.. compiler☆32Updated last year
- Open source process design kit for 28nm open process☆51Updated 11 months ago
- An open-source benchmark for generating design RTL with natural language☆97Updated 4 months ago
- ☆25Updated 11 months ago
- LLM Agent for Hardware Description Language☆19Updated 2 weeks ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆20Updated 8 months ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆30Updated last year
- ☆76Updated 2 months ago
- ☆51Updated 5 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆80Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆75Updated last month
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆17Updated 4 years ago
- Collection of digital hardware modules & projects (benchmarks)☆51Updated 4 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆25Updated 4 years ago
- ☆139Updated 5 months ago
- A configurable SRAM generator☆47Updated 2 months ago
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 4 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆53Updated 2 weeks ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated last month
- SRAM☆21Updated 4 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated last month
- A toolchain for rapid design space exploration of chiplet architectures☆45Updated 2 weeks ago
- ☆43Updated 5 years ago
- Dataset for ML-guided Accelerator Design☆36Updated 4 months ago