Fast Symbolic Repair of Hardware Design Code
☆40Jan 20, 2025Updated last year
Alternatives and similar repositories for rtl-repair
Users that are interested in rtl-repair are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Feb 26, 2025Updated last year
- Automated Repair of Verilog Hardware Descriptions☆40Jan 16, 2025Updated last year
- [ICCAD'26] Forbench: Symbolic Simulation Helps Make Your Testbench More Formal☆15Oct 31, 2026Updated last week
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 3 years ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆15Feb 6, 2021Updated 5 years ago
- ☆17Apr 27, 2026Updated 6 months ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 11 months ago
- A Lean-embedded framework to verify Verilog modules☆17Oct 6, 2026Updated last month
- Certify Model Checking Witnesses in AIGER☆14Oct 16, 2026Updated 3 weeks ago
- ☆13Oct 25, 2026Updated last week
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆72Oct 28, 2024Updated 2 years ago
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated 2 months ago
- Research project from UCI's AICPS lab: using GNNs to enable hardware security and prevent hardware trojans☆10Mar 31, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆21Jun 12, 2024Updated 2 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- An advanced circuit-based sat solver☆39Feb 24, 2025Updated last year
- FastPoly: An Efficient Polynomial Package for the Verification of Integer Arithmetic Circuits☆14Aug 5, 2025Updated last year
- ☆21Updated this week
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆16Aug 30, 2023Updated 3 years ago
- work in progress, playing around with btor2 in rust☆16Updated this week
- ☆10Sep 29, 2024Updated 2 years ago
- ☆17Jun 12, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning (TACAS 2026)☆10Oct 9, 2025Updated last year
- Translate Chisel hardware design code to Scala simulation code.☆15May 15, 2025Updated last year
- ☆15Dec 6, 2023Updated 2 years ago
- ☆11Nov 19, 2015Updated 10 years ago
- ☆18Nov 9, 2022Updated 3 years ago
- Fuzzing processor simulations with taint tracking.☆15Aug 24, 2025Updated last year
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- A tool for checking the contract satisfaction for hardware designs☆12Jul 21, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Equivalence Verification Checking for Code Transformation via Equality Saturation☆13Jun 1, 2026Updated 5 months ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆118Updated this week
- ☆18Jul 11, 2021Updated 5 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆46Apr 3, 2025Updated last year
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆33Jun 23, 2025Updated last year
- ☆16Sep 14, 2020Updated 6 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago