Fast Symbolic Repair of Hardware Design Code
☆39Jan 20, 2025Updated last year
Alternatives and similar repositories for rtl-repair
Users that are interested in rtl-repair are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Automated Repair of Verilog Hardware Descriptions☆39Jan 16, 2025Updated last year
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- ☆15Feb 6, 2021Updated 5 years ago
- A Lean-embedded framework to verify Verilog modules☆15Jul 3, 2026Updated 3 weeks ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 8 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- work in progress, playing around with btor2 in rust☆15Updated this week
- Research project from UCI's AICPS lab: using GNNs to enable hardware security and prevent hardware trojans☆10Mar 31, 2021Updated 5 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆64Oct 28, 2024Updated last year
- A collection of datapath circuit design and verification benchmarks☆19Jul 9, 2026Updated 2 weeks ago
- ☆19Dec 21, 2020Updated 5 years ago
- ☆21Jun 12, 2024Updated 2 years ago
- An advanced circuit-based sat solver☆39Feb 24, 2025Updated last year
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆29Jun 23, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆15Sep 14, 2020Updated 5 years ago
- ☆15Dec 6, 2023Updated 2 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆113Updated this week
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆44Apr 3, 2025Updated last year
- ☆18Nov 19, 2023Updated 2 years ago
- ☆18Jul 11, 2021Updated 5 years ago
- ☆17Apr 27, 2026Updated 3 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆11May 24, 2019Updated 7 years ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆19Jan 17, 2026Updated 6 months ago
- ☆14Jun 12, 2024Updated 2 years ago
- ☆19Oct 17, 2024Updated last year
- ☆49May 18, 2024Updated 2 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 7 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆59Jan 8, 2025Updated last year
- ☆26Feb 19, 2026Updated 5 months ago
- Connecting bv_decide to SMTLIB.☆15Jul 21, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- LLM-Assisted Hardware Formal Verification Tool☆111Jul 13, 2026Updated 2 weeks ago
- ☆14Jan 3, 2018Updated 8 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆44Jul 17, 2024Updated 2 years ago
- ☆26Mar 1, 2023Updated 3 years ago
- (WIP) Open-source Rust gate-level EDA infrastructure: parsers and databases☆21May 2, 2026Updated 2 months ago