ekiwi / rtl-repair
Fast Symbolic Repair of Hardware Design Code
☆22Updated 3 months ago
Alternatives and similar repositories for rtl-repair:
Users that are interested in rtl-repair are comparing it to the libraries listed below
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆20Updated 3 months ago
- Equivalence checking with Yosys☆42Updated 2 weeks ago
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆17Updated 6 months ago
- ☆13Updated last month
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆27Updated 5 months ago
- ☆11Updated 3 years ago
- Hardware Formal Verification Tool☆45Updated this week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆81Updated last year
- ☆18Updated 9 months ago
- This is a python repo for flattening Verilog☆16Updated 2 weeks ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 5 years ago
- ☆13Updated 4 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆13Updated 3 weeks ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆33Updated 2 months ago
- CoreIR Symbolic Analyzer☆71Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆17Updated 2 years ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated last week
- A Formal Verification Framework for Chisel☆18Updated last year
- 21st century electronic design automation tools, written in Rust.☆30Updated this week
- Collection for submission (Hardware Model Checking Benchmark)☆9Updated 6 months ago
- A hardware synthesis framework with multi-level paradigm☆38Updated 3 months ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆26Updated last year
- Project Repo for the Simulator Independent Coverage Research☆19Updated 2 years ago
- Source files to reproduce the results shown for A-QED at DAC 2020☆9Updated 4 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆45Updated 7 months ago
- ☆12Updated 4 years ago