Alternatives and similar repositories for verilog-wishbone:

Users that are interested in verilog-wishbone are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆130Updated 2 months ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆114Updated last month
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆69Updated 2 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆94Updated 2 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆131Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated last month
• ldoolitt / vhd2vl
  ☆130Updated 3 months ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆65Updated 2 months ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆119Updated 3 weeks ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆34Updated 11 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆101Updated 3 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆146Updated last month
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆40Updated 5 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆117Updated 8 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆61Updated 2 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆26Updated 2 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆79Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 2 months ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆85Updated 8 months ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆76Updated 11 months ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆120Updated 2 years ago
• jamieiles / uart
  Verilog UART
  ☆148Updated 11 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated last month
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆31Updated 2 weeks ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆101Updated last year