Alternatives and similar repositories for verilog-wishbone

Users that are interested in verilog-wishbone are comparing it to the libraries listed below

• ldoolitt / vhd2vl
  ☆136Updated 9 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 3 months ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆88Updated 2 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆157Updated 6 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 7 months ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆77Updated 2 years ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆127Updated 2 years ago
• hypernyan / eth_vlg
  ☆74Updated 3 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆80Updated 3 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆126Updated 3 months ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆90Updated last year
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆94Updated 4 years ago
• open-design / riscv-soc-cores
  ☆38Updated 4 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆155Updated 2 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆64Updated 2 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆108Updated 4 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆143Updated 2 weeks ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated last month
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆67Updated 7 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated this week
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated last week
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆95Updated 5 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆37Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆29Updated 2 years ago