MIPS CPU implemented in Verilog
☆657Oct 3, 2017Updated 8 years ago
Alternatives and similar repositories for mips-cpu
Users that are interested in mips-cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A very primitive but hopefully self-educational CPU in Verilog☆155Jan 21, 2015Updated 11 years ago
- MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.☆25Oct 3, 2018Updated 7 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆627Mar 15, 2018Updated 8 years ago
- A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cach…☆78Nov 4, 2024Updated last year
- mor1kx - an OpenRISC 1000 processor IP core☆588Jun 6, 2026Updated 2 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- 5 stage pipelined MIPS-32 processor☆56Apr 20, 2020Updated 6 years ago
- 奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）☆131Nov 13, 2019Updated 6 years ago
- CPU microarchitecture, step by step☆212Nov 1, 2020Updated 5 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆208Oct 9, 2019Updated 6 years ago
- A Verilog HDL model of the MOS 6502 CPU☆386Apr 8, 2023Updated 3 years ago
- Verilog library for ASIC and FPGA designers☆1,436May 8, 2024Updated 2 years ago
- 一步一步写MIPS CPU☆880Jun 5, 2026Updated 2 months ago
- Verilog UART☆582Feb 27, 2025Updated last year
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.☆19Jul 29, 2015Updated 11 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,851Mar 24, 2021Updated 5 years ago
- Icarus Verilog☆3,624Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,371Jul 31, 2026Updated last month
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,604Updated this week
- A implementation of a 32-bit single cycle MIPS processor in Verilog.☆22Nov 23, 2020Updated 5 years ago
- RISC-V CPU Core (RV32IM)☆1,779Sep 18, 2021Updated 4 years ago
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old Uni…☆61Jul 29, 2015Updated 11 years ago
- A MIPS32 CPU implemented by VHDL☆30Apr 28, 2013Updated 13 years ago
- A small, light weight, RISC CPU soft core☆1,579Aug 19, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆128Feb 19, 2016Updated 10 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- synthesiseable ieee 754 floating point library in verilog☆756Mar 13, 2023Updated 3 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆146Apr 3, 2020Updated 6 years ago
- Educational 16-bit MIPS Processor☆18Feb 16, 2019Updated 7 years ago
- A Pi emulating a GameBoy sounds cheap. What about an FPGA?☆542Dec 10, 2022Updated 3 years ago
- A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding☆165May 20, 2022Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆44May 22, 2020Updated 6 years ago
- An implementation of MIPS single cycle datapath in Verilog.☆16Mar 11, 2012Updated 14 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- The Easy 8-bit Processor☆187Jun 9, 2014Updated 12 years ago
- The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.…☆48Aug 11, 2014Updated 12 years ago
- GPGPU microprocessor architecture☆2,220Nov 8, 2024Updated last year
- Verilog cache implementation of 4-way FIFO 16k Cache☆21Dec 8, 2012Updated 13 years ago
- 通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器☆211Mar 2, 2022Updated 4 years ago
- Must-have verilog systemverilog modules☆2,017Mar 12, 2026Updated 5 months ago
- Verilog Ethernet components for FPGA implementation☆3,078Feb 27, 2025Updated last year