MIPS CPU implemented in Verilog
☆660Oct 3, 2017Updated 9 years ago
Alternatives and similar repositories for mips-cpu
Users that are interested in mips-cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A very primitive but hopefully self-educational CPU in Verilog☆155Jan 21, 2015Updated 11 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆632Mar 15, 2018Updated 8 years ago
- MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.☆25Oct 3, 2018Updated 8 years ago
- A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cach…☆79Nov 4, 2024Updated last year
- CPU microarchitecture, step by step☆214Nov 1, 2020Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- mor1kx - an OpenRISC 1000 processor IP core☆593Jun 6, 2026Updated 4 months ago
- 5 stage pipelined MIPS-32 processor☆56Apr 20, 2020Updated 6 years ago
- Verilog library for ASIC and FPGA designers☆1,440May 8, 2024Updated 2 years ago
- 奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）☆131Nov 13, 2019Updated 6 years ago
- Verilog UART☆591Feb 27, 2025Updated last year
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.☆20Jul 29, 2015Updated 11 years ago
- 一步一步写MIPS CPU☆886Jun 5, 2026Updated 4 months ago
- A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding☆165May 20, 2022Updated 4 years ago
- A Verilog HDL model of the MOS 6502 CPU☆391Apr 8, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RISC-V CPU Core (RV32IM)☆1,812Sep 18, 2021Updated 5 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆209Oct 9, 2019Updated 7 years ago
- A implementation of a 32-bit single cycle MIPS processor in Verilog.☆22Nov 23, 2020Updated 5 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆146Apr 3, 2020Updated 6 years ago
- synthesiseable ieee 754 floating point library in verilog☆763Mar 13, 2023Updated 3 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,398Sep 7, 2026Updated last month
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,632Oct 12, 2026Updated 3 weeks ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,855Mar 24, 2021Updated 5 years ago
- A 32-bit MIPS processor developed in Verilog.☆11Aug 10, 2014Updated 12 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A small, light weight, RISC CPU soft core☆1,597Sep 16, 2026Updated last month
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old Uni…☆60Jul 29, 2015Updated 11 years ago
- Icarus Verilog☆3,711Updated this week
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆392Jan 12, 2018Updated 8 years ago
- A convolutional neural network implemented in hardware (verilog)☆167Sep 7, 2017Updated 9 years ago
- Various HDL (Verilog) IP Cores☆939Jul 1, 2021Updated 5 years ago
- 32-bit Superscalar RISC-V CPU☆1,329Sep 18, 2021Updated 5 years ago
- Learn how to design digital systems and synthesize them into an FPGA using only opensource tools☆871Apr 15, 2020Updated 6 years ago
- Parallel Array of Simple Cores. Multicore processor.☆101May 16, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A look ahead, round-robing parametrized arbiter written in Verilog.☆44May 22, 2020Updated 6 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆21Dec 8, 2012Updated 13 years ago
- Educational 16-bit MIPS Processor☆17Feb 16, 2019Updated 7 years ago
- Verilog Ethernet components for FPGA implementation☆3,142Feb 27, 2025Updated last year
- GPGPU microprocessor architecture☆2,232Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,301Oct 13, 2026Updated 3 weeks ago
- Verilog PCI express components☆1,675Apr 26, 2024Updated 2 years ago