MIPS CPU implemented in Verilog
☆646Oct 3, 2017Updated 8 years ago
Alternatives and similar repositories for mips-cpu
Users that are interested in mips-cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A very primitive but hopefully self-educational CPU in Verilog☆153Jan 21, 2015Updated 11 years ago
- MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.☆25Oct 3, 2018Updated 7 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆619Mar 15, 2018Updated 8 years ago
- 5 stage pipelined MIPS-32 processor☆57Apr 20, 2020Updated 6 years ago
- A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cach…☆76Nov 4, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- mor1kx - an OpenRISC 1000 processor IP core☆583Aug 21, 2025Updated 8 months ago
- 奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）☆130Nov 13, 2019Updated 6 years ago
- CPU microarchitecture, step by step☆208Nov 1, 2020Updated 5 years ago
- 一步一步写MIPS CPU☆859Aug 4, 2021Updated 4 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆199Oct 9, 2019Updated 6 years ago
- A Verilog HDL model of the MOS 6502 CPU☆376Apr 8, 2023Updated 3 years ago
- Verilog library for ASIC and FPGA designers☆1,410May 8, 2024Updated last year
- Verilog UART☆561Feb 27, 2025Updated last year
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.☆19Jul 29, 2015Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,840Mar 24, 2021Updated 5 years ago
- Icarus Verilog☆3,426Apr 28, 2026Updated last week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,127Jun 27, 2024Updated last year
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,541Apr 27, 2026Updated last week
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old Uni…☆62Jul 29, 2015Updated 10 years ago
- RISC-V CPU Core (RV32IM)☆1,712Sep 18, 2021Updated 4 years ago
- A small, light weight, RISC CPU soft core☆1,532Dec 8, 2025Updated 4 months ago
- A implementation of a 32-bit single cycle MIPS processor in Verilog.☆21Nov 23, 2020Updated 5 years ago
- A MIPS32 CPU implemented by VHDL☆30Apr 28, 2013Updated 13 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆127Feb 19, 2016Updated 10 years ago
- The Easy 8-bit Processor☆187Jun 9, 2014Updated 11 years ago
- synthesiseable ieee 754 floating point library in verilog☆734Mar 13, 2023Updated 3 years ago
- A Pi emulating a GameBoy sounds cheap. What about an FPGA?☆521Dec 10, 2022Updated 3 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Educational 16-bit MIPS Processor☆18Feb 16, 2019Updated 7 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆141Apr 3, 2020Updated 6 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43May 22, 2020Updated 5 years ago
- GPGPU microprocessor architecture☆2,189Nov 8, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.…☆45Aug 11, 2014Updated 11 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding☆164May 20, 2022Updated 3 years ago
- An implementation of MIPS single cycle datapath in Verilog.☆17Mar 11, 2012Updated 14 years ago
- Verilog Ethernet components for FPGA implementation☆2,947Feb 27, 2025Updated last year
- 32-bit Superscalar RISC-V CPU☆1,239Sep 18, 2021Updated 4 years ago
- 通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器☆210Mar 2, 2022Updated 4 years ago