MIPS CPU implemented in Verilog
☆643Oct 3, 2017Updated 8 years ago
Alternatives and similar repositories for mips-cpu
Users that are interested in mips-cpu are comparing it to the libraries listed below
Sorting:
- A very primitive but hopefully self-educational CPU in Verilog☆151Jan 21, 2015Updated 11 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆616Mar 15, 2018Updated 7 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆577Aug 21, 2025Updated 6 months ago
- MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.☆25Oct 3, 2018Updated 7 years ago
- 5 stage pipelined MIPS-32 processor☆57Apr 20, 2020Updated 5 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆196Oct 9, 2019Updated 6 years ago
- A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cach…☆75Nov 4, 2024Updated last year
- Verilog library for ASIC and FPGA designers☆1,392May 8, 2024Updated last year
- 一步一步写MIPS CPU☆854Aug 4, 2021Updated 4 years ago
- CPU microarchitecture, step by step☆207Nov 1, 2020Updated 5 years ago
- 奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）☆130Nov 13, 2019Updated 6 years ago
- Verilog UART☆536Feb 27, 2025Updated last year
- Icarus Verilog☆3,338Feb 25, 2026Updated last week
- A Verilog HDL model of the MOS 6502 CPU☆367Apr 8, 2023Updated 2 years ago
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.☆19Jul 29, 2015Updated 10 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,986Jun 27, 2024Updated last year
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,815Mar 24, 2021Updated 4 years ago
- synthesiseable ieee 754 floating point library in verilog☆721Mar 13, 2023Updated 2 years ago
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old Uni…☆61Jul 29, 2015Updated 10 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,493Jan 7, 2026Updated last month
- RISC-V CPU Core (RV32IM)☆1,646Sep 18, 2021Updated 4 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- A small, light weight, RISC CPU soft core☆1,514Dec 8, 2025Updated 2 months ago
- Parallel Array of Simple Cores. Multicore processor.☆100May 16, 2019Updated 6 years ago
- 32-bit Superscalar RISC-V CPU☆1,179Sep 18, 2021Updated 4 years ago
- Verilog Ethernet components for FPGA implementation☆2,865Feb 27, 2025Updated last year
- The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.…☆45Aug 11, 2014Updated 11 years ago
- GPGPU microprocessor architecture☆2,179Nov 8, 2024Updated last year
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆684Jul 16, 2025Updated 7 months ago
- Must-have verilog systemverilog modules☆1,934Feb 19, 2026Updated last week
- A implementation of a 32-bit single cycle MIPS processor in Verilog.☆20Nov 23, 2020Updated 5 years ago
- The Easy 8-bit Processor☆187Jun 9, 2014Updated 11 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,032Feb 11, 2026Updated 3 weeks ago
- A Pi emulating a GameBoy sounds cheap. What about an FPGA?☆514Dec 10, 2022Updated 3 years ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆126Feb 19, 2016Updated 10 years ago
- Learn how to design digital systems and synthesize them into an FPGA using only opensource tools☆847Apr 15, 2020Updated 5 years ago
- Various HDL (Verilog) IP Cores☆876Jul 1, 2021Updated 4 years ago
- Educational 16-bit MIPS Processor☆18Feb 16, 2019Updated 7 years ago
- 通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器☆208Mar 2, 2022Updated 4 years ago