MIPS CPU implemented in Verilog
☆654Oct 3, 2017Updated 8 years ago
Alternatives and similar repositories for mips-cpu
Users that are interested in mips-cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A very primitive but hopefully self-educational CPU in Verilog☆154Jan 21, 2015Updated 11 years ago
- MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.☆25Oct 3, 2018Updated 7 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆626Mar 15, 2018Updated 8 years ago
- A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cach…☆76Nov 4, 2024Updated last year
- mor1kx - an OpenRISC 1000 processor IP core☆587Jun 6, 2026Updated 2 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 5 stage pipelined MIPS-32 processor☆55Apr 20, 2020Updated 6 years ago
- 奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)☆131Nov 13, 2019Updated 6 years ago
- CPU microarchitecture, step by step☆210Nov 1, 2020Updated 5 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆206Oct 9, 2019Updated 6 years ago
- A Verilog HDL model of the MOS 6502 CPU☆386Apr 8, 2023Updated 3 years ago
- Verilog library for ASIC and FPGA designers☆1,436May 8, 2024Updated 2 years ago
- 一步一步写MIPS CPU☆879Jun 5, 2026Updated 2 months ago
- Verilog UART☆575Feb 27, 2025Updated last year
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.☆19Jul 29, 2015Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,850Mar 24, 2021Updated 5 years ago
- Icarus Verilog☆3,593Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,333Jul 31, 2026Updated 2 weeks ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,599May 12, 2026Updated 3 months ago
- A implementation of a 32-bit single cycle MIPS processor in Verilog.☆22Nov 23, 2020Updated 5 years ago
- RISC-V CPU Core (RV32IM)☆1,765Sep 18, 2021Updated 4 years ago
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old Uni…☆61Jul 29, 2015Updated 11 years ago
- A small, light weight, RISC CPU soft core☆1,573Dec 8, 2025Updated 8 months ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆127Feb 19, 2016Updated 10 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- synthesiseable ieee 754 floating point library in verilog☆753Mar 13, 2023Updated 3 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆146Apr 3, 2020Updated 6 years ago
- Educational 16-bit MIPS Processor☆18Feb 16, 2019Updated 7 years ago
- A Pi emulating a GameBoy sounds cheap. What about an FPGA?☆542Dec 10, 2022Updated 3 years ago
- A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding☆165May 20, 2022Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆44May 22, 2020Updated 6 years ago
- An implementation of MIPS single cycle datapath in Verilog.☆16Mar 11, 2012Updated 14 years ago
- The Easy 8-bit Processor☆187Jun 9, 2014Updated 12 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.…☆47Aug 11, 2014Updated 12 years ago
- GPGPU microprocessor architecture☆2,215Nov 8, 2024Updated last year
- Verilog cache implementation of 4-way FIFO 16k Cache☆21Dec 8, 2012Updated 13 years ago
- 通过学习《自己动手写CPU》,将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水线结构),简化成单指令周期实现的处理器☆211Mar 2, 2022Updated 4 years ago
- Must-have verilog systemverilog modules☆2,007Mar 12, 2026Updated 5 months ago
- Verilog Ethernet components for FPGA implementation☆3,065Feb 27, 2025Updated last year
- 32-bit Superscalar RISC-V CPU☆1,289Sep 18, 2021Updated 4 years ago