A huge collection of VHDL/Verilog open-source IP cores scraped from the web
☆637Jan 18, 2023Updated 3 years ago
Alternatives and similar repositories for ip-cores
Users that are interested in ip-cores are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- few python scripts to clone all IP cores from opencores.org☆32Jan 8, 2024Updated 2 years ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆172Oct 27, 2015Updated 11 years ago
- Various HDL (Verilog) IP Cores☆941Jul 1, 2021Updated 5 years ago
- Latex source files of the open-source book FREE RANGE VHDL☆365Mar 5, 2025Updated last year
- Verilog library for ASIC and FPGA designers☆1,439May 8, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- HDL libraries and projects☆2,052Updated this week
- Must-have verilog systemverilog modules☆2,031Mar 12, 2026Updated 7 months ago
- Verilog AXI components for FPGA implementation☆2,171Feb 27, 2025Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,749Updated this week
- Verilog Ethernet components for FPGA implementation☆3,145Feb 27, 2025Updated last year
- Hardware Description Languages☆1,184Oct 27, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,482Updated this week
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆607Jul 30, 2025Updated last year
- An Open-source FPGA IP Generator☆1,167Updated this week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆632Mar 15, 2018Updated 8 years ago
- Code generation tool for control and status registers☆476Sep 11, 2026Updated last month
- A huge VHDL library for FPGA and digital ASIC development☆481Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,303Oct 13, 2026Updated 3 weeks ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,398Sep 7, 2026Updated 2 months ago
- Verilog PCI express components☆1,676Apr 26, 2024Updated 2 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆1,012Aug 28, 2026Updated 2 months ago
- Common SystemVerilog components☆815Sep 18, 2026Updated last month
- A Verilog implementation of Multi-bit-throughput LFSR with an detailed document about LFSRs for HW design engineers☆10Jan 2, 2026Updated 10 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆85Feb 8, 2020Updated 6 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆220Updated this week
- Build your hardware, easily!☆4,190Updated this week
- 10Gb Ethernet Switch☆279Sep 17, 2026Updated last month
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,162Updated this week
- Universal utility for programming FPGA☆1,786Updated this week
- Multi-platform nightly builds of open source digital design and verification tools☆1,808Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆160Oct 21, 2026Updated 2 weeks ago
- ☆18Sep 16, 2020Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Send video/audio over HDMI on an FPGA☆1,314Jul 13, 2026Updated 3 months ago
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆696Jul 16, 2025Updated last year
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆241Sep 14, 2023Updated 3 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,186Updated this week
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆23Aug 6, 2025Updated last year
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆802Jun 15, 2024Updated 2 years ago