Alternatives and similar repositories for PoC

Users that are interested in PoC are comparing it to the libraries listed below

• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆406Updated last week
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆248Updated last month
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆789Updated last month
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆587Updated 4 months ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆396Updated last week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆710Updated 2 weeks ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆189Updated 2 years ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,336Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆602Updated last month
• pyuvm / pyuvm
  The UVM written in Python
  ☆450Updated 2 months ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆640Updated last week
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆219Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆663Updated 2 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆279Updated last year
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆440Updated 3 months ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆281Updated 5 years ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆517Updated 2 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆416Updated last week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆453Updated 3 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆309Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆654Updated last week
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆446Updated last year
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆369Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆467Updated last week
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆293Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆342Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆828Updated 3 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated last month
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆281Updated this week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆830Updated 6 months ago