Alternatives and similar repositories for PoC:

Users that are interested in PoC are comparing it to the libraries listed below

• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆758Updated last week
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆385Updated 3 weeks ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆234Updated this week
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆372Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆518Updated last week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆662Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,239Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆639Updated 3 months ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆183Updated last year
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆775Updated 6 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆588Updated 2 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆570Updated last week
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆350Updated this week
• pyuvm / pyuvm
  The UVM written in Python
  ☆400Updated last month
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,198Updated 2 weeks ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆575Updated 7 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆547Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆388Updated 5 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆318Updated last month
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆399Updated 2 weeks ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆267Updated 5 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆244Updated last month
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,246Updated 9 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆280Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆734Updated 3 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆443Updated last year
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆656Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆306Updated this week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆264Updated 4 years ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆512Updated 4 months ago