Alternatives and similar repositories for PoC

Users that are interested in PoC are comparing it to the libraries listed below

• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆402Updated this week
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆245Updated 2 weeks ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆784Updated last week
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆393Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆582Updated 4 months ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆189Updated 2 years ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆707Updated 3 weeks ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,325Updated this week
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆367Updated last week
• pyuvm / pyuvm
  The UVM written in Python
  ☆449Updated last month
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆819Updated 5 months ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆214Updated last month
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆279Updated 5 years ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆634Updated 3 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated last month
• lowRISC / style-guides
  lowRISC Style Guides
  ☆448Updated 2 months ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆513Updated 2 years ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆292Updated last week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆438Updated 3 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆659Updated 2 months ago
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆736Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆598Updated last week
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆279Updated last year
• enjoy-digital / litepcie
  Small footprint and configurable PCIe core
  ☆575Updated last month
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆818Updated 2 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆309Updated last year
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆175Updated this week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆464Updated 2 weeks ago
• Digilent / vivado-boards
  ☆459Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆649Updated this week