zephray / VerilogBoyLinks
A Pi emulating a GameBoy sounds cheap. What about an FPGA?
☆493Updated 2 years ago
Alternatives and similar repositories for VerilogBoy
Users that are interested in VerilogBoy are comparing it to the libraries listed below
Sorting:
- iCESugar FPGA Board (base on iCE40UP5k)☆392Updated 2 months ago
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆642Updated 5 months ago
- A Verilog HDL model of the MOS 6502 CPU☆343Updated 2 years ago
- NES in Verilog☆197Updated 4 years ago
- A simple, basic, formally verified UART controller☆304Updated last year
- 80186 compatible SystemVerilog CPU core and FPGA reference design☆398Updated last year
- Linux on LiteX-VexRiscv☆642Updated 2 weeks ago
- A small, light weight, RISC CPU soft core☆1,420Updated 4 months ago
- 720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)☆279Updated 4 years ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆435Updated 9 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆667Updated 3 weeks ago
- SERV - The SErial RISC-V CPU☆1,600Updated 2 weeks ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆918Updated 7 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆475Updated 3 years ago
- FPGA-based Nintendo Entertainment System Emulator☆267Updated last year
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆294Updated last month
- Bus bridges and other odds and ends☆568Updated 2 months ago
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆659Updated this week
- Multi-platform nightly builds of open source digital design and verification tools☆1,081Updated this week
- Various HDL (Verilog) IP Cores☆813Updated 3 years ago
- Project Apicula 🐝: bitstream documentation for Gowin FPGAs☆561Updated this week
- Small footprint and configurable DRAM core☆418Updated 3 weeks ago
- VeeR EH1 core☆883Updated 2 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,300Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆639Updated last month
- A simple RISC-V processor for use in FPGA designs.☆275Updated 10 months ago
- 32-bit Superscalar RISC-V CPU☆1,036Updated 3 years ago
- A Linux-capable RISC-V multicore for and by the world☆709Updated last month
- A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals☆239Updated 6 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆325Updated 3 years ago