A collection of demonstration digital filters
☆180Jan 18, 2024Updated 2 years ago
Alternatives and similar repositories for dspfilters
Users that are interested in dspfilters are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Digital Interpolation Techniques Applied to Digital Signal Processing☆71Jun 24, 2024Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆123Jan 18, 2024Updated 2 years ago
- Wishbone controlled I2C controllers☆63Aug 10, 2026Updated 2 months ago
- RTL Verilog library for various DSP modules☆103Feb 17, 2022Updated 4 years ago
- A wishbone controlled scope for FPGA's☆95Jan 12, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog digital signal processing components☆197Oct 30, 2022Updated 4 years ago
- A series of CORDIC related projects☆128Nov 12, 2024Updated last year
- Verilog FPGA code : including experimental DSP audio processor☆14Dec 1, 2020Updated 5 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- A wishbone controlled PWM (audio) controller☆19Jan 16, 2024Updated 2 years ago
- FIR implemention with Verilog☆51May 18, 2019Updated 7 years ago
- A simple, basic, formally verified UART controller☆356Jan 29, 2024Updated 2 years ago
- Wishbone SATA Controller☆28Sep 17, 2026Updated last month
- Repository gathering basic modules for CDC purpose☆64Dec 31, 2019Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆87Nov 8, 2025Updated 11 months ago
- A utility for Composing FPGA designs from Peripherals☆194Aug 31, 2026Updated 2 months ago
- A wishbone controlled FM transmitter hack☆25Jan 16, 2024Updated 2 years ago
- 10Gb Ethernet Switch☆279Sep 17, 2026Updated last month
- A small, light weight, RISC CPU soft core☆1,597Sep 16, 2026Updated last month
- A configurable C++ generator of pipelined Verilog FFT cores☆269Apr 18, 2024Updated 2 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Various HDL (Verilog) IP Cores☆939Jul 1, 2021Updated 5 years ago
- HDL libraries and projects☆2,048Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 12 years ago
- Bus bridges and other odds and ends☆714Sep 11, 2026Updated last month
- USB capture IP☆27Jun 6, 2020Updated 6 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- A basic Soft(Gate)ware Defined Radio architecture☆106Jan 18, 2024Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 9 years ago
- Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.☆12Aug 9, 2019Updated 7 years ago
- A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.☆12May 3, 2014Updated 12 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆632Mar 15, 2018Updated 8 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 11 years ago
- Verilog RTL Design☆53Sep 4, 2021Updated 5 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆165Feb 27, 2025Updated last year
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆696Jul 16, 2025Updated last year
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆48Apr 15, 2024Updated 2 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 7 years ago
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆484Jan 29, 2023Updated 3 years ago