A collection of demonstration digital filters
☆167Jan 18, 2024Updated 2 years ago
Alternatives and similar repositories for dspfilters
Users that are interested in dspfilters are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Digital Interpolation Techniques Applied to Digital Signal Processing☆68Jun 24, 2024Updated last year
- RTL Verilog library for various DSP modules☆95Feb 17, 2022Updated 4 years ago
- A collection of phase locked loop (PLL) related projects☆118Jan 18, 2024Updated 2 years ago
- A wishbone controlled scope for FPGA's☆88Jan 12, 2024Updated 2 years ago
- A series of CORDIC related projects☆121Nov 12, 2024Updated last year
- Verilog digital signal processing components☆172Oct 30, 2022Updated 3 years ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- A wishbone controlled PWM (audio) controller☆18Jan 16, 2024Updated 2 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- Wishbone controlled I2C controllers☆57Nov 12, 2024Updated last year
- A simple, basic, formally verified UART controller☆329Jan 29, 2024Updated 2 years ago
- A configurable C++ generator of pipelined Verilog FFT cores☆256Apr 18, 2024Updated last year
- A small, light weight, RISC CPU soft core☆1,526Dec 8, 2025Updated 3 months ago
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago
- 10Gb Ethernet Switch☆258Oct 16, 2025Updated 5 months ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 10 years ago
- Wishbone SATA Controller☆25Oct 16, 2025Updated 5 months ago
- Demo Sources for Learning Spinal HDL☆16Dec 5, 2022Updated 3 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆618Mar 15, 2018Updated 8 years ago
- HDL libraries and projects☆1,878Updated this week
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Feb 27, 2025Updated last year
- Various HDL (Verilog) IP Cores☆879Jul 1, 2021Updated 4 years ago
- Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.☆12Aug 9, 2019Updated 6 years ago
- FIR implemention with Verilog☆50May 18, 2019Updated 6 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆118Updated this week
- a USB2 highspeed device core, written in amaranth HDL☆53Sep 17, 2024Updated last year
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆33Oct 31, 2021Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated last year
- A wishbone controlled FM transmitter hack☆24Jan 16, 2024Updated 2 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆78Nov 8, 2025Updated 4 months ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆34Aug 7, 2021Updated 4 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Apr 15, 2024Updated last year
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- A utility for Composing FPGA designs from Peripherals☆187Dec 23, 2024Updated last year
- Bus bridges and other odds and ends☆650Mar 10, 2026Updated last week
- Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)☆31Aug 14, 2020Updated 5 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆685Jul 16, 2025Updated 8 months ago