Alternatives and similar repositories for dspfilters

Users that are interested in dspfilters are comparing it to the libraries listed below

• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆127Updated 5 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆116Updated 2 years ago
• ZipCPU / dblclockfft
  A configurable C++ generator of pipelined Verilog FFT cores
  ☆253Updated last year
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆121Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆170Updated 3 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆86Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated 2 months ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆89Updated 7 years ago
• mattvenn / fpga-sdft
  sliding DFT for FPGA, targetting Lattice ICE40 1k
  ☆76Updated 5 years ago
• ZipCPU / interpolation
  Digital Interpolation Techniques Applied to Digital Signal Processing
  ☆67Updated last year
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆197Updated last week
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆115Updated last week
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆58Updated 9 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated last week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆130Updated 8 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆81Updated this week
• HDLForBeginners / Examples
  ☆118Updated 2 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆124Updated 2 years ago
• yol / ethernet_mac
  Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
  ☆177Updated 2 years ago
• ldoolitt / vhd2vl
  ☆140Updated this week
• dawsonjon / FPGA-radio
  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
  ☆114Updated 9 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆119Updated 4 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆160Updated 11 months ago
• Avnet / hdl
  ☆114Updated 10 months ago
• PyFPGA / pyfpga
  A Python package to use FPGA development tools programmatically.
  ☆144Updated 10 months ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆185Updated this week
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆97Updated 5 years ago