t-crest / patmosLinks
Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
☆153Updated last month
Alternatives and similar repositories for patmos
Users that are interested in patmos are comparing it to the libraries listed below
Sorting:
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184Updated 9 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Updated 5 years ago
- A time-predictable processor for mixed-criticality systems☆60Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆238Updated last year
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆174Updated last week
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- OmniXtend cache coherence protocol☆82Updated 8 months ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- ☆104Updated 3 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- RISC-V Formal Verification Framework☆178Updated 3 weeks ago
- ☆87Updated last week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆119Updated 8 months ago
- The specification for the FIRRTL language☆62Updated last week
- Mutation Cover with Yosys (MCY)☆91Updated last week
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- FPGA tool performance profiling☆105Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 7 months ago
- Main page☆129Updated 6 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 3 years ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- FPGA Assembly (FASM) Parser and Generator☆99Updated 3 years ago
- The multi-core cluster of a PULP system.☆111Updated last week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 months ago
- A SystemVerilog source file pickler.☆60Updated last year