t-crest / patmosLinks
Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
☆145Updated this week
Alternatives and similar repositories for patmos
Users that are interested in patmos are comparing it to the libraries listed below
Sorting:
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆178Updated 2 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆159Updated 5 years ago
- A time-predictable processor for mixed-criticality systems☆59Updated 8 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆109Updated 2 months ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- ☆85Updated last month
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 8 months ago
- ☆103Updated 3 years ago
- Main page☆126Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuits☆120Updated 2 years ago
- RISC-V Formal Verification Framework☆143Updated this week
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 months ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆162Updated last month
- A SystemVerilog source file pickler.☆59Updated 9 months ago
- FPGA tool performance profiling☆102Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆73Updated last year
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- OmniXtend cache coherence protocol☆82Updated last month
- The multi-core cluster of a PULP system.☆105Updated last week
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- Chisel/Firrtl execution engine☆153Updated 11 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- The specification for the FIRRTL language☆60Updated this week
- Mutation Cover with Yosys (MCY)☆85Updated 3 weeks ago