schoeberl / chisel-emptyLinks
An almost empty chisel project as a starting point for hardware design
☆31Updated 4 months ago
Alternatives and similar repositories for chisel-empty
Users that are interested in chisel-empty are comparing it to the libraries listed below
Sorting:
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆40Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆56Updated 3 years ago
- Advanced Architecture Labs with CVA6☆61Updated last year
- ☆49Updated 6 years ago
- ☆22Updated 2 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated 2 weeks ago
- eyeriss-chisel3☆40Updated 3 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆17Updated 3 weeks ago
- ☆33Updated 2 months ago
- 关于移植模型至gemmini的文档☆27Updated 3 years ago
- ☆28Updated 4 years ago
- ☆67Updated 3 months ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- Chisel Cheatsheet☆33Updated 2 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- ☆18Updated 2 years ago
- ☆64Updated 2 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 3 weeks ago
- Pick your favorite language to verify your chip.☆49Updated last week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- RISC-V Matrix Specification☆22Updated 6 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- ☆47Updated last month
- StateMover is a checkpoint-based debugging framework for FPGAs.☆19Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- ☆29Updated last month
- ☆30Updated 5 months ago