An almost empty chisel project as a starting point for hardware design
☆35Jan 27, 2025Updated last year
Alternatives and similar repositories for chisel-empty
Users that are interested in chisel-empty are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Lipsi: Probably the Smallest Processor in the World☆88Apr 15, 2024Updated last year
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆230Feb 19, 2026Updated last month
- IOPMP IP☆24Jul 11, 2025Updated 8 months ago
- An implementation of RISC-V☆50Dec 11, 2025Updated 3 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆604Aug 9, 2024Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Chisel examples and code snippets☆275Aug 1, 2022Updated 3 years ago
- Hardware design with Chisel☆35Feb 9, 2023Updated 3 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- Research about dataflow architecture☆12Nov 30, 2023Updated 2 years ago
- Digital Design with Chisel☆905Mar 19, 2026Updated 3 weeks ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- ☆39Oct 21, 2025Updated 5 months ago
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 2 years ago
- Lab Material for CAE☆44Jan 6, 2026Updated 3 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, A…☆47Nov 8, 2023Updated 2 years ago
- A vision transformer based framework for classifying executable images as benign or malicious☆10Mar 19, 2024Updated 2 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆72Nov 7, 2024Updated last year
- A dynamic verification library for Chisel.☆160Nov 9, 2024Updated last year
- SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...☆31Dec 9, 2021Updated 4 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A Style Guide for the Chisel Hardware Construction Language☆109Jul 16, 2021Updated 4 years ago
- A Tiny Processor Core☆114Jul 14, 2025Updated 8 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- The home of the Chisel3 website☆21May 24, 2024Updated last year
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆16May 23, 2019Updated 6 years ago
- Verilog implementation of a simple riscv cpu☆18Oct 28, 2021Updated 4 years ago
- A template project for beginning new Chisel work☆696Feb 24, 2026Updated last month
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- ☆24Oct 24, 2022Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆164May 10, 2025Updated 11 months ago
- Convert json descriptions of quant algorithms to verilog HDL.☆13Jul 3, 2020Updated 5 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 11 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆88Nov 26, 2025Updated 4 months ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆27Jan 19, 2026Updated 2 months ago
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago