schoeberl / chisel-emptyLinks
An almost empty chisel project as a starting point for hardware design
☆33Updated last year
Alternatives and similar repositories for chisel-empty
Users that are interested in chisel-empty are comparing it to the libraries listed below
Sorting:
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆46Updated 2 years ago
- ☆58Updated 6 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- Advanced Architecture Labs with CVA6☆73Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆79Updated 2 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- An open-source UCIe implementation☆82Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆33Updated last week
- eyeriss-chisel3☆40Updated 3 years ago
- ☆70Updated 11 months ago
- Chisel Learning Journey☆111Updated 2 years ago
- ☆22Updated 2 years ago
- ☆32Updated 6 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆95Updated last month
- Public release☆58Updated 6 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- A repository for SystemC Learning examples☆73Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- SystemC training aimed at TLM.☆35Updated 5 years ago
- A verilog implementation for Network-on-Chip☆81Updated 7 years ago
- ☆63Updated 9 months ago
- The official NaplesPU hardware code repository☆21Updated 6 years ago
- ☆31Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Updated last month
- Modular Multi-ported SRAM-based Memory☆31Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆73Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated 2 years ago
- ☆19Updated 2 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 2 weeks ago