Alternatives and similar repositories for riscv-chisel-book

Users that are interested in riscv-chisel-book are comparing it to the libraries listed below

• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆45Updated 4 years ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆641Updated 2 weeks ago
• rhysd / riscv32-cpu-chisel
  Learning how to make RISC-V 32bit CPU with Chisel
  ☆67Updated 3 years ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆360Updated 7 years ago
• shioyadan / advanced-computer-organization
  ☆162Updated 9 months ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆251Updated 2 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆577Updated 9 months ago
• onikiri / onikiri2
  ☆39Updated 9 months ago
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 5 years ago
• NNgen / nngen
  NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
  ☆352Updated last year
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆201Updated this week
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆158Updated 6 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆838Updated 3 weeks ago
• arm-university / Introduction-to-Computer-Architecture-Education-Kit
  Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm …
  ☆274Updated last week
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆145Updated this week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆118Updated 3 weeks ago
• vaj / riscv-os
  A tiny educational OS for RISC-V
  ☆22Updated 7 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆137Updated 5 years ago
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆30Updated 10 months ago
• tomabou / cpu_core
  ☆9Updated 5 years ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 9 months ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆147Updated 2 years ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆148Updated 3 months ago
• nananapo / veryl-riscv-book
  Let's write RISC-V CPU in Veryl!
  ☆44Updated this week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆114Updated 3 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆68Updated 6 months ago
• ciniml / seccamp_riscv_cpu
  セキュリティ・キャンプ 2022-2024 RISC-V CPU自作ゼミ 資料置き場
  ☆37Updated last month
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆457Updated last year
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆59Updated 3 years ago
• msyksphinz-self / support_ca_llvm_book
  ☆142Updated 10 months ago