Alternatives and similar repositories for riscv-chisel-book

Users that are interested in riscv-chisel-book are comparing it to the libraries listed below

• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆45Updated 4 years ago
• rhysd / riscv32-cpu-chisel
  Learning how to make RISC-V 32bit CPU with Chisel
  ☆69Updated 4 years ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆674Updated 2 months ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆368Updated 8 years ago
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆165Updated 4 months ago
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 5 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆108Updated 10 months ago
• arm-university / Introduction-to-Computer-Architecture-Education-Kit
  Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm …
  ☆290Updated 6 months ago
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆108Updated 3 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆600Updated last year
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆32Updated last year
• nananapo / veryl-riscv-book
  Let's write RISC-V CPU in Veryl!
  ☆57Updated this week
• NNgen / nngen
  NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
  ☆357Updated 2 years ago
• onikiri / onikiri2
  ☆39Updated last year
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆263Updated 3 years ago
• diningyo / dirv
  This is my first trial project for designing RISC-V in Chisel
  ☆17Updated last year
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆218Updated 3 weeks ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆144Updated this week
• PyHDI / veriloggen
  Veriloggen: A Mixed-Paradigm Hardware Construction Framework
  ☆323Updated last year
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆499Updated last year
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆879Updated 2 weeks ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆150Updated 2 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆160Updated last week
• HirokiNakahara / FPGA_lecture
  Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.
  ☆28Updated 4 years ago
• vaj / riscv-os
  A tiny educational OS for RISC-V
  ☆26Updated last year
• aquaxis / FPGAMAG18
  FPGA Magazine No.18 - RISC-V
  ☆17Updated 8 years ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆150Updated 3 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆150Updated 6 years ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆232Updated last year
• ryuz / jelly
  Original FPGA platform
  ☆70Updated last week