riscv-boom / riscv-coremark
Setup scripts and files needed to compile CoreMark on RISC-V
☆65Updated 8 months ago
Alternatives and similar repositories for riscv-coremark:
Users that are interested in riscv-coremark are comparing it to the libraries listed below
- AIA IP compliant with the RISC-V AIA spec☆38Updated 2 months ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- The multi-core cluster of a PULP system.☆89Updated last week
- ☆32Updated 3 weeks ago
- RISC-V Nexus Trace TG documentation and reference code☆50Updated 3 months ago
- ☆42Updated 3 years ago
- ☆90Updated last year
- RISC-V Matrix Specification☆21Updated 4 months ago
- RISC-V Verification Interface☆87Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆70Updated this week
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- RISC-V IOMMU Specification☆112Updated this week
- Unit tests generator for RVV 1.0☆80Updated 2 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆143Updated 3 weeks ago
- ☆86Updated 2 years ago
- ☆82Updated last month
- CVA6 SDK containing RISC-V tools and Buildroot☆63Updated 9 months ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- ☆46Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆63Updated 7 months ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆14Updated last year
- Advanced Architecture Labs with CVA6☆56Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆90Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆103Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆50Updated 2 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆89Updated 3 weeks ago