Alternatives and similar repositories for riscv-coremark:

Users that are interested in riscv-coremark are comparing it to the libraries listed below

• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆85Updated last week
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆61Updated 8 months ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆61Updated last year
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆36Updated last month
• riscv / riscv-CMOs
  ☆85Updated 2 years ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆79Updated last week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆109Updated this week
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆53Updated last year
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆54Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆66Updated last week
• riscv / riscv-aia
  ☆86Updated last week
• pulp-platform / fpu
  ☆41Updated 6 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated 11 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆87Updated this week
• chipsalliance / uvm-verilator
  ☆88Updated last year
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆50Updated 2 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆49Updated 5 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆37Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆85Updated last month
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆78Updated this week
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆19Updated 3 months ago
• oprecomp / DDR4_controller
  ☆53Updated 4 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆111Updated 2 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆137Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆80Updated last week
• Xilinx / pcie-model
  PCI Express controller model
  ☆50Updated 2 years ago
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 5 years ago
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated 3 weeks ago