Alternatives and similar repositories for riscv-coremark

Users that are interested in riscv-coremark are comparing it to the libraries listed below

• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆44Updated 6 months ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆101Updated 3 weeks ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated this week
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆72Updated last month
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆174Updated last month
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆57Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆46Updated 3 years ago
• riscv / riscv-CMOs
  ☆89Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆119Updated last month
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆89Updated last week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆106Updated last week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last week
• riscv / riscv-test-env
  ☆49Updated 3 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆100Updated 2 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆90Updated last week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆65Updated 7 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated this week
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated last month
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆51Updated 7 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• chipsalliance / uvm-verilator
  ☆97Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆114Updated this week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆24Updated 6 years ago