Alternatives and similar repositories for riscv-aia:

Users that are interested in riscv-aia are comparing it to the libraries listed below

• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆17Updated 2 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 8 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆37Updated last year
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆19Updated last year
• riscv / riscv-aia
  ☆86Updated this week
• riscv-non-isa / iopmp-spec
  This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…
  ☆26Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆88Updated this week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 10 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆109Updated last week
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆50Updated 2 months ago
• riscv / riscv-CMOs
  ☆85Updated 2 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated 11 months ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆48Updated 3 years ago
• chipsalliance / tilelink
  ☆28Updated 3 months ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆49Updated this week
• pulp-platform / ace
  ☆11Updated 6 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆63Updated 9 months ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 3 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆74Updated last year
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆25Updated last year
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 4 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆79Updated this week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆37Updated 10 months ago
• chipsalliance / uvm-verilator
  ☆88Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆38Updated 2 years ago
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆19Updated 3 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆68Updated last week
• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆16Updated 2 weeks ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆25Updated 5 months ago