AIA IP compliant with the RISC-V AIA spec
☆46Jan 27, 2025Updated last year
Alternatives and similar repositories for riscv-aia
Users that are interested in riscv-aia are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V IOMMU Demo (Linux & Bao)☆24Dec 5, 2023Updated 2 years ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆45Nov 24, 2025Updated 4 months ago
- RISC-V IOMMU in verilog☆23Jun 18, 2022Updated 3 years ago
- Linux kernel source tree☆21Mar 26, 2026Updated 3 weeks ago
- ☆99Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆117Sep 24, 2025Updated 6 months ago
- ☆13Nov 20, 2025Updated 5 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆38May 4, 2024Updated last year
- IOPMP IP☆25Jul 11, 2025Updated 9 months ago
- A guide on how to build and use a set of Bao guest configurations for various platforms☆52Mar 21, 2026Updated 3 weeks ago
- The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…☆21Mar 31, 2026Updated 3 weeks ago
- RISC-V IOMMU Specification☆157Apr 2, 2026Updated 2 weeks ago
- ☆14Nov 9, 2023Updated 2 years ago
- ☆27Dec 30, 2025Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Rocket Chip Generator☆13Jul 31, 2021Updated 4 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 2 years ago
- Talk is cheap. Show me the code.☆22Oct 28, 2024Updated last year
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆69Apr 7, 2026Updated 2 weeks ago
- ☆32Apr 13, 2026Updated last week
- ☆22Mar 27, 2026Updated 3 weeks ago
- Message Signaled Interrupts for RISC-V☆28Sep 15, 2024Updated last year
- RISC-V Confidential VM Extension☆15Jan 14, 2026Updated 3 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RISC-V fast interrupt controller☆34Nov 20, 2025Updated 5 months ago
- Native Linux KVM tool☆14Feb 4, 2026Updated 2 months ago
- hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine☆59Nov 30, 2023Updated 2 years ago
- Coffer is a RISC-V trusted execution environment developed in Rust.☆20Mar 3, 2022Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆204Apr 8, 2026Updated last week
- This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …☆67Mar 7, 2026Updated last month
- CROSSCON-Hypervisor, a Lightweight Hypervisor☆22Dec 19, 2025Updated 4 months ago
- MultiZone® Security TEE for Arm® Cortex®-M is the quick and safe way to add security and separation to any Cortex-M based device. MultiZo…☆14Aug 21, 2023Updated 2 years ago
- RISC-V Configuration Validator☆82Mar 28, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…☆39Mar 7, 2026Updated last month
- The official NaplesPU hardware code repository☆24Jul 27, 2019Updated 6 years ago
- Bao, a Lightweight Static Partitioning Hypervisor☆523Updated this week
- RISC-V Directed Test Framework and Compliance Suite, RiESCUE☆60Apr 9, 2026Updated last week
- ☆14Jun 7, 2021Updated 4 years ago
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Dec 1, 2024Updated last year
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆60Apr 3, 2026Updated 2 weeks ago