Alternatives and similar repositories for ssith-aws-fpga

Users that are interested in ssith-aws-fpga are comparing it to the libraries listed below

• BSVLang / Main
  Main page
  ☆128Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 5 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆153Updated this week
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated 6 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆147Updated last month
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆178Updated last year
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 6 months ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆84Updated 3 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆212Updated 7 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆232Updated 10 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆201Updated last year
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆115Updated 4 months ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆80Updated 3 years ago
• antmicro / sv-bugpoint
  ☆30Updated 3 weeks ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆182Updated 2 weeks ago
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆55Updated 4 years ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆110Updated 9 years ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆325Updated 3 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆58Updated 11 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆60Updated last week
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆87Updated this week
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆180Updated this week
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 3 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆245Updated last year
• SpinalHDL / NaxRiscv
  ☆296Updated 2 weeks ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆268Updated 2 weeks ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆163Updated 5 years ago