Alternatives and similar repositories for ssith-aws-fpga

Users that are interested in ssith-aws-fpga are comparing it to the libraries listed below

• BSVLang / Main
  Main page
  ☆129Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆181Updated 8 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆176Updated last week
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆152Updated last week
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆116Updated 3 weeks ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆223Updated 10 months ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated last week
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆89Updated this week
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆231Updated last week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆185Updated last year
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆329Updated 3 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆119Updated 8 months ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆111Updated 9 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆81Updated 3 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆176Updated 2 years ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆208Updated this week
• antmicro / sv-bugpoint
  ☆34Updated 2 weeks ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆186Updated last week
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆92Updated 3 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆237Updated last year
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆60Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆206Updated last year
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆56Updated 5 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• fangism / hackt
  Hierarchical Asynchronous Circuit Kompiler Toolkit
  ☆24Updated last month
• ArgonDesign / alogic
  Alogic is a Medium Level Synthesis language for digital logic that compiles swiftly into standard Verilog-2005 for implementation in ASIC…
  ☆17Updated 4 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆161Updated 10 months ago
• stnolting / fpga_puf
  Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
  ☆138Updated 3 years ago