Alternatives and similar repositories for corev-llvm-project:

Users that are interested in corev-llvm-project are comparing it to the libraries listed below

• riscv / riscv-bfloat16
  ☆34Updated 9 months ago
• riscv-non-isa / riscv-semihosting
  ☆28Updated 2 months ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆12Updated last year
• gvsoc / gvsoc
  ☆18Updated this week
• embecosm / embecosm-toolchain-releases
  ☆16Updated last month
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆50Updated 3 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 11 months ago
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆33Updated last month
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆28Updated 2 months ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆23Updated last year
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆37Updated 3 weeks ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆31Updated last week
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆32Updated 2 years ago
• antmicro / verilator-old-archived
  ☆22Updated 2 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆45Updated last month
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆30Updated last year
• pulp-platform / gvsoc
  Pulp virtual platform
  ☆23Updated 2 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆54Updated this week
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆76Updated last month
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆34Updated 11 months ago
• riscv / virtual-memory
  ☆36Updated 3 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆39Updated last year
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• riscvarchive / riscv-zicond
  The ISA specification for the ZiCondOps extension.
  ☆19Updated last year
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆35Updated last year
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆49Updated this week
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆89Updated 3 weeks ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆80Updated 4 months ago