Description of a RISC-V architecture based on MIPS 3000
☆14Apr 24, 2023Updated 2 years ago
Alternatives and similar repositories for RiVer_SoC
Users that are interested in RiVer_SoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An unnecessarily tiny and minimal implementation of GPT-2 in NumPy.☆11Feb 12, 2023Updated 3 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- A minimalistic Operating System relying on a basic bootloader and a small kernel capable of loading a given application☆12Jul 11, 2018Updated 7 years ago
- Tiny Tapeout GDS Action (using OpenLane)☆21Mar 25, 2026Updated 2 weeks ago
- The WooKey project manifest repository, use repo init -u https://github.com/wookey-project/manifest.git☆17May 28, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆13Jul 11, 2018Updated 7 years ago
- A VHDL implementation of SipHash☆13Feb 19, 2015Updated 11 years ago
- TEMPORARY FORK of the riscv-compliance repository☆32Mar 31, 2021Updated 5 years ago
- Game Boy Instruction Tester☆27Feb 17, 2023Updated 3 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Mar 30, 2026Updated last week
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆10Apr 29, 2024Updated last year
- coursera code☆13Jun 27, 2013Updated 12 years ago
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.☆42Nov 17, 2014Updated 11 years ago
- The code for an FPGA softcore comparison☆11Jun 21, 2020Updated 5 years ago
- Hardware implementation of the SipHash short-inout PRF☆17Apr 3, 2025Updated last year
- Learn how to create your own 32-bit system from scratch.☆14Feb 15, 2022Updated 4 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 5 months ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- ESP32-based portable Multi-Sensor Pod [in development]☆10Dec 3, 2023Updated 2 years ago
- Implementation of a RISC-V CPU in Verilog.☆17Mar 2, 2025Updated last year
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆15Jun 15, 2016Updated 9 years ago
- RISC-V Core Local Interrupt Controller (CLINT)☆30Mar 10, 2026Updated 3 weeks ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- System-on-Chip Interconnection Network - Simulation Environment (front-end)☆15Oct 5, 2023Updated 2 years ago
- 🌄 RISC-V Ecosystem Landscape: a living document that developers, investors, vendors, researchers and others can use as a resource on the…☆21Updated this week
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated last month
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Mar 30, 2026Updated last week
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆17Mar 3, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Synthesizable Uxn CPU☆17Jul 14, 2022Updated 3 years ago
- RISC-V Configuration Validator☆82Mar 28, 2025Updated last year
- Timing Sidechannel workshop☆30Nov 25, 2013Updated 12 years ago
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 6 years ago
- The ISA specification for the ZiCondOps extension.☆19Mar 21, 2024Updated 2 years ago
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 2 years ago
- UNSUPPORTED INTERNAL toolchain builds☆48Feb 24, 2026Updated last month