lovisXII / RiVer_SoCLinks
Description of a RISC-V architecture based on MIPS 3000
☆13Updated 2 years ago
Alternatives and similar repositories for RiVer_SoC
Users that are interested in RiVer_SoC are comparing it to the libraries listed below
Sorting:
- MathLib DAC 2023 version☆12Updated last year
- Open source ISS and logic RISC-V 32 bit project☆57Updated 2 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Summer School Week 1 & 2 repo☆11Updated 3 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆19Updated 2 years ago
- ☆40Updated last year
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆24Updated 6 years ago
- A Barrel design of RV32I☆22Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆23Updated last year
- CMake based hardware build system☆30Updated 2 weeks ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆13Updated this week
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- ☆16Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- ☆14Updated 4 months ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated last year
- ☆30Updated 3 weeks ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆31Updated 4 years ago
- Complete tutorial code.☆21Updated last year
- An open-source 32-bit RISC-V soft-core processor☆36Updated 3 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- APB UVC ported to Verilator☆11Updated last year