lovisXII / RiVer_SoCLinks
Description of a RISC-V architecture based on MIPS 3000
☆13Updated 2 years ago
Alternatives and similar repositories for RiVer_SoC
Users that are interested in RiVer_SoC are comparing it to the libraries listed below
Sorting:
- A Barrel design of RV32I☆22Updated 2 years ago
- MathLib DAC 2023 version☆13Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- ☆40Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- ☆14Updated 7 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- The purpose of the repo is to support CORE-V Wally architectural verification☆15Updated last week
- CMake based hardware build system☆32Updated this week
- APB UVC ported to Verilator☆11Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 9 months ago
- DUTH RISC-V Microprocessor☆22Updated 11 months ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 2 weeks ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆22Updated 5 months ago
- LIS Network-on-Chip Implementation☆33Updated 9 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated last month
- A Python package for generating HDL wrappers and top modules for HDL sources☆39Updated last week
- ☆30Updated 3 weeks ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Updated 11 months ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago