Description of a RISC-V architecture based on MIPS 3000
☆14Apr 24, 2023Updated 3 years ago
Alternatives and similar repositories for RiVer_SoC
Users that are interested in RiVer_SoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An unnecessarily tiny and minimal implementation of GPT-2 in NumPy.☆11Feb 12, 2023Updated 3 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- A minimalistic Operating System relying on a basic bootloader and a small kernel capable of loading a given application☆12Jul 11, 2018Updated 8 years ago
- The WooKey project manifest repository, use repo init -u https://github.com/wookey-project/manifest.git☆16May 28, 2021Updated 5 years ago
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 7 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆14Jul 11, 2018Updated 8 years ago
- TEMPORARY FORK of the riscv-compliance repository☆34Mar 31, 2021Updated 5 years ago
- coursera code☆13Jun 27, 2013Updated 13 years ago
- ModuOS is a hobby operating system written in C and x86-64 assembly.☆15Jul 10, 2026Updated last week
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Jun 19, 2026Updated last month
- A VHDL implementation of SipHash☆13Feb 19, 2015Updated 11 years ago
- Game Boy Instruction Tester☆28Feb 17, 2023Updated 3 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 2 months ago
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.☆43Nov 17, 2014Updated 11 years ago
- Hardware implementation of the SipHash short-inout PRF☆18Apr 3, 2025Updated last year
- The code for an FPGA softcore comparison☆11Jun 21, 2020Updated 6 years ago
- Learn how to create your own 32-bit system from scratch.☆14Feb 15, 2022Updated 4 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆15Jun 15, 2016Updated 10 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆19Nov 16, 2023Updated 2 years ago
- ESP32-based portable Multi-Sensor Pod [in development]☆10Dec 3, 2023Updated 2 years ago
- RISC-V Core Local Interrupt Controller (CLINT)☆32Apr 8, 2026Updated 3 months ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Implementation of a RISC-V CPU in Verilog.☆18Jun 27, 2026Updated 3 weeks ago
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆21May 4, 2017Updated 9 years ago
- Tiny Tapeout GDS Action (using LibreLane)☆23Updated this week
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- System-on-Chip Interconnection Network - Simulation Environment (front-end)☆16Oct 5, 2023Updated 2 years ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated 4 months ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Jun 19, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A Reconfigurable RISC-V Core for Approximate Computing☆131May 30, 2025Updated last year
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- Timing Sidechannel workshop☆30Nov 25, 2013Updated 12 years ago
- Synthesizable Uxn CPU☆18Jul 14, 2022Updated 4 years ago
- RISC-V Configuration Validator☆82Apr 16, 2026Updated 3 months ago
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 3 years ago
- UNSUPPORTED INTERNAL toolchain builds☆48Feb 24, 2026Updated 4 months ago