Alternatives and similar repositories for rvv-atg:

Users that are interested in rvv-atg are comparing it to the libraries listed below

• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆73Updated last month
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 6 months ago
• sequencer / arithmetic
  ☆32Updated this week
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆34Updated this week
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• riscv / riscv-CMOs
  ☆83Updated 2 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆73Updated last month
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆64Updated this week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆54Updated last year
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆49Updated 4 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆102Updated last month
• riscv / riscv-aclint
  ☆42Updated 3 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 11 months ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆108Updated 2 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆84Updated this week
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆37Updated last year
• lizhirui / DreamCoreV2
  ☆21Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆35Updated 2 years ago
• chipsalliance / tilelink
  ☆27Updated last month
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆64Updated 5 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆74Updated last year
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆48Updated 3 weeks ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆54Updated last year
• riscv / riscv-bfloat16
  ☆33Updated 6 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆86Updated last week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated 11 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆124Updated 3 weeks ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• chipsalliance / t1
  ☆130Updated this week