Alternatives and similar repositories for intrinsics-viewer

Users that are interested in intrinsics-viewer are comparing it to the libraries listed below

• ocxtal / insn_bench_aarch64
  Instruction latency & throughput profiler for AArch64
  ☆39Updated last month
• revec / VectorBench
  Benchmarks for auto-vectorization and revectorization, including both hand-vectorized and scalar code
  ☆30Updated 6 years ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆128Updated this week
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated last month
• travisdowns / robsize
  ROB size testing utility
  ☆157Updated 3 years ago
• dtcxzyw / llvm-ub-aware-interpreter
  UB-aware interpreter for LLVM debugging
  ☆31Updated last week
• ychen306 / vegen
  ☆31Updated 2 years ago
• twest820 / AVX-512
  AVX-512 documentation beyond what Intel provides
  ☆55Updated last year
• dougallj / asil
  ☆33Updated last year
• InstLatx64 / InstLatX64_Demo
  InstLatX64_Demo
  ☆44Updated last month
• cdl-saarland / rv
  RV: A Unified Region Vectorizer for LLVM
  ☆112Updated 4 months ago
• mshockwave / SQLGen
  Generate SQL from TableGen code - This is part of the tutorial "How to write a TableGen backend" in 2021 LLVM Developers' Meeting.
  ☆33Updated 2 years ago
• ucb-bar / berkeley-softfloat-3
  SoftFloat release 3
  ☆300Updated 6 months ago
• llvm / eudsl
  Embedded Universal DSL: a good DSL for us, by us
  ☆45Updated last week
• ChipsandCheese / Microbenchmarks
  Trying to figure various CPU things out
  ☆86Updated last year
• kitbarton / LLVMLoopOptTutorial
  Tutorial for LLVM Dev Conference 2019.
  ☆15Updated 5 years ago
• cucapra / turnt
  simple snapshot-style integration testing for commands
  ☆72Updated 4 months ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆48Updated last year
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆92Updated 2 weeks ago
• pfalcon / ssabook
  Mirror of InriaForge SSABook repository: https://gforge.inria.fr/projects/ssabook/ (was scheduled for retirement at the end of 2020, was …
  ☆142Updated 5 years ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆152Updated last week
• makslevental / mmlir
  A minimal (really) out-of-tree MLIR example
  ☆45Updated last month
• Lancern / mlir-gccjit
  MLIR dialect for libgccjit
  ☆21Updated 9 months ago
• andreas-abel / uiCA
  uops.info Code Analyzer
  ☆290Updated last year
• ucb-bar / berkeley-testfloat-3
  TestFloat release 3
  ☆69Updated 6 months ago
• ria-jit / ria-jit
  Lightweight and performant dynamic binary translation for RISC–V code on x86–64
  ☆60Updated 4 years ago
• dtcxzyw / llvm-opt-benchmark
  An LLVM IR dataset for data-driven compiler optimization research
  ☆65Updated this week
• nfinit / ansibench
  A selection of ANSI C benchmarks and programs useful as benchmarks
  ☆92Updated last year
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆77Updated this week