Alternatives and similar repositories for sse2rvv

Users that are interested in sse2rvv are comparing it to the libraries listed below

• howjmay / neon2rvv
  A translator from ARM NEON intrinsics to RISCV-V Extension implementation
  ☆34Updated 10 months ago
• camel-cdr / rvv-bench-results
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
  ☆33Updated 3 weeks ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆44Updated last year
• RISCVtestbed / rvv-rollback
  Translate RISC-V Vector Assembly from v1.0 to v0.7
  ☆34Updated 10 months ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆118Updated 3 weeks ago
• XUANTIE-RV / thead-extension-spec
  XuanTie vendor extension Instruction Set spec
  ☆39Updated 3 weeks ago
• vortexgpgpu / pocl
  a clone of POCL that includes RISC-V newlib devices support and Vortex
  ☆42Updated 3 months ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆76Updated last week
• riscv-admin / riscv-ovpsim
  ☆62Updated 4 years ago
• s-holst / tinyrv
  A tiny RISC-V instruction decoder and instruction set simulator
  ☆21Updated last week
• LLNL / zhw
  ZFP Hardware Implementation
  ☆13Updated 2 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• atrosinenko / memtest86-plus-riscv
  Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)
  ☆16Updated 5 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆101Updated last month
• leos313 / DOOM_FPGA
  Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
  ☆18Updated 5 years ago
• openhwgroup / core-v-sw
  Main Repo for the OpenHW Group Software Task Group
  ☆17Updated 3 months ago
• InstLatx64 / InstLatX64_Demo
  InstLatX64_Demo
  ☆43Updated last month
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆100Updated 2 years ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆26Updated 3 weeks ago
• dzaima / intrinsics-viewer
  x86-64, ARM, and RVV intrinsics viewer
  ☆46Updated 2 months ago
• vortexgpgpu / NVPTX-SPIRV-Translator
  The translator that supports translating NVPTX to SPIR-V. This translator is modified from LLVM-SPIR-V Translator.
  ☆40Updated 3 years ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆50Updated 4 years ago
• UCTECHIP / rocket_chip_vpu
  ☆11Updated 4 years ago
• riscvarchive / riscv-zicond
  The ISA specification for the ZiCondOps extension.
  ☆19Updated last year
• OpenXiangShan / nexus-am
  ☆35Updated last month
• oprecomp / flexfloat
  C library for the emulation of reduced-precision floating point types
  ☆51Updated 2 years ago
• ToNi3141 / RasterIX
  OpenGL 1.x implementation for FPGAs
  ☆91Updated last week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆58Updated 2 weeks ago
• riscv-non-isa / server-soc
  The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate …
  ☆24Updated last week
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆47Updated last month