Alternatives and similar repositories for riscv-arch-test:

Users that are interested in riscv-arch-test are comparing it to the libraries listed below

• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆475Updated this week
• riscv-software-src / riscv-tests
  ☆943Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆272Updated last year
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆494Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆852Updated last year
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆948Updated 3 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆313Updated 8 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,019Updated 2 weeks ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,069Updated 3 weeks ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆724Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆578Updated this week
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆609Updated 3 weeks ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆245Updated 3 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆456Updated 2 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆644Updated 3 months ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆259Updated this week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆307Updated 2 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆669Updated 4 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆660Updated this week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆701Updated 6 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆592Updated 2 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆564Updated 6 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆899Updated 3 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,478Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆595Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 3 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆861Updated 3 years ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆311Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,216Updated this week
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆209Updated 11 months ago