Alternatives and similar repositories for riscv-arch-test:

Users that are interested in riscv-arch-test are comparing it to the libraries listed below

• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆479Updated last month
• riscv-software-src / riscv-tests
  ☆963Updated last month
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆514Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆274Updated last year
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆262Updated this week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆318Updated 9 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,084Updated last month
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,033Updated last month
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆865Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 4 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆595Updated 2 weeks ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆669Updated last month
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆565Updated 7 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆709Updated 3 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆469Updated last month
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆975Updated 3 years ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆615Updated this week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆206Updated 3 weeks ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆735Updated last week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆904Updated 4 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆598Updated 2 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆677Updated 3 weeks ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆868Updated 4 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆648Updated 4 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆309Updated 3 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆329Updated this week
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆209Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆269Updated 2 weeks ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 4 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆414Updated 2 weeks ago