FelipeFFerreira / ITA-CORES
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
☆44Updated last year
Alternatives and similar repositories for ITA-CORES:
Users that are interested in ITA-CORES are comparing it to the libraries listed below
- A pipelined RISC-V processor☆51Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆75Updated last week
- RISC-V Nox core☆62Updated 7 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆60Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆61Updated this week
- Wishbone interconnect utilities☆39Updated last month
- Open source ISS and logic RISC-V 32 bit project☆43Updated 3 months ago
- ☆59Updated 3 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆37Updated this week
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- FPGA based microcomputer sandbox for software and RTL experimentation☆53Updated this week
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆50Updated 2 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- ☆33Updated 4 months ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated 11 months ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆89Updated 6 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆24Updated 3 weeks ago
- A collection of debugging busses developed and presented at zipcpu.com☆39Updated last year
- Reusable Verilog 2005 components for FPGA designs☆40Updated 3 weeks ago
- An open-source HDL register code generator fast enough to run in real time.☆58Updated this week
- End-to-End Open-Source I2C GPIO Expander☆31Updated last month
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆83Updated last year
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆51Updated 2 weeks ago
- Spen's Official OpenOCD Mirror☆48Updated last week
- ☆41Updated last year
- A compact, configurable RISC-V core☆11Updated last month
- SAR ADC on tiny tapeout☆39Updated last month
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆27Updated 6 years ago
- Extensible FPGA control platform☆59Updated last year