FelipeFFerreira / ITA-CORESView external linksLinks
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
☆55Nov 16, 2023Updated 2 years ago
Alternatives and similar repositories for ITA-CORES
Users that are interested in ITA-CORES are comparing it to the libraries listed below
Sorting:
- Implementation of a RISC-V CPU in Verilog.☆17Mar 2, 2025Updated 11 months ago
- RISC-V Playground on Nandland Go☆16Mar 2, 2023Updated 2 years ago
- A Risc-V SoC for Tiny Tapeout☆48Dec 2, 2025Updated 2 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Feb 3, 2026Updated 2 weeks ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆167Dec 29, 2025Updated last month
- HF-RISC SoC☆39Nov 10, 2025Updated 3 months ago
- Playground for VGA projects on Tiny Tapeout☆69Feb 9, 2026Updated last week
- World's first Nintendo 3DS emulator for Apple devices based on Citra.☆18Apr 7, 2023Updated 2 years ago
- A Video/Camera image (over VGA) to oscilloscope X/Y mode streaming tool☆20Jan 30, 2025Updated last year
- Verilog hardware abstraction library☆45Feb 4, 2026Updated last week
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆33Updated this week
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆35Nov 6, 2025Updated 3 months ago
- RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K☆43Apr 11, 2024Updated last year
- RISC-V Nox core☆71Jul 22, 2025Updated 6 months ago
- A catalog of my old-school GFX effects☆43Jan 30, 2024Updated 2 years ago
- Logarithmic DAC for AY8913 and SN76489 programmable sound generators (Done as part of Zero To ASIC Analog course)☆11Jun 1, 2024Updated last year
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆17Nov 19, 2019Updated 6 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated 8 months ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Top level for the November shuttle☆12Nov 20, 2021Updated 4 years ago
- A simple Makefile based project for WCH's CHV32V range of RISCV uControllers☆14Jun 22, 2025Updated 7 months ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆14Feb 26, 2025Updated 11 months ago
- 32-bit RISC-V microcontroller for embedded, FPGA and ASIC applications☆189Jan 31, 2026Updated 2 weeks ago
- Library of open source PDKs☆65Feb 3, 2026Updated 2 weeks ago
- ☆15Dec 17, 2025Updated 2 months ago
- MangoPI MQ-Quad board Linux (Allwinner H616)☆12Apr 6, 2023Updated 2 years ago
- Arrow Matrix Decomposition - Communication-Efficient Distributed Sparse Matrix Multiplication☆15Mar 25, 2024Updated last year
- Parametrized RTL benchmark suite☆23Feb 6, 2026Updated last week
- design and verification of asynchronous circuits☆43Jan 18, 2026Updated 3 weeks ago
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 11 years ago
- An example model of a Network Processing Unit using the PFPSim framework.☆13Aug 23, 2016Updated 9 years ago
- Website for the OpenROAD tutorial held at the MICRO 2022 conference☆33Oct 6, 2022Updated 3 years ago
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- ☆14Sep 23, 2020Updated 5 years ago
- ☆13Dec 1, 2024Updated last year
- Another size-optimized RISC-V CPU for your consideration.☆59Feb 1, 2026Updated 2 weeks ago
- ☆17Oct 7, 2025Updated 4 months ago