Alternatives and similar repositories for ITA-CORES:

Users that are interested in ITA-CORES are comparing it to the libraries listed below

• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆50Updated last year
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆52Updated last week
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆57Updated 2 months ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 6 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆73Updated this week
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆82Updated 4 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated 8 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆41Updated 2 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆49Updated 2 weeks ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆37Updated 2 months ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆49Updated this week
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆32Updated 2 weeks ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆77Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆72Updated 9 months ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 2 months ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆39Updated last year
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆21Updated 3 months ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆51Updated last year
• efabless / caravel_board
  ☆33Updated 2 months ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆86Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 8 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆65Updated 9 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆63Updated 2 years ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated this week
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆37Updated last year
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆65Updated 7 months ago
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆35Updated this week
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆20Updated last year