Alternatives and similar repositories for nox

Users that are interested in nox are comparing it to the libraries listed below

• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated 3 weeks ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆68Updated 7 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 9 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆45Updated 3 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆63Updated 6 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated last week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆126Updated last week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆35Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last month
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆73Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆57Updated 2 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆55Updated last month
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆77Updated last month
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆122Updated 2 months ago
• pulp-platform / cheshire-ihp130-o
  ☆47Updated 4 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆47Updated last year
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆106Updated 4 years ago
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆47Updated 2 weeks ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆73Updated 2 weeks ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆138Updated 2 weeks ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated last week
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆41Updated 2 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆89Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆73Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆104Updated 2 months ago