Alternatives and similar repositories for nox:

Users that are interested in nox are comparing it to the libraries listed below

• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆73Updated this week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆49Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 8 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆67Updated 10 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆44Updated 3 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆71Updated 2 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆42Updated 3 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆69Updated this week
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆58Updated 3 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆73Updated 2 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆42Updated 2 months ago
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆33Updated last week
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 7 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 5 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆58Updated 2 months ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 2 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆62Updated last month
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆78Updated 4 months ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆106Updated 4 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆62Updated this week
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆43Updated 2 weeks ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 4 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last week
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆38Updated last month
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆29Updated 3 months ago