Alternatives and similar repositories for riscado-v

Users that are interested in riscado-v are comparing it to the libraries listed below

• klessydra / F03x
  A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance
  ☆15Updated last year
• klessydra / T03x
  A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores
  ☆18Updated 5 months ago
• Saanlima / RISC5Verilog_psram
  ☆15Updated 4 years ago
• ghent360 / riscvOnColorlight-5A-75B
  RISC-V soft core running on Colorlight 5B-74B.
  ☆37Updated 4 years ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆44Updated last year
• atthecodeface / cdl_hardware
  CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc
  ☆16Updated 5 years ago
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆75Updated 2 years ago
• klessydra / T02x
  A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores
  ☆23Updated last year
• trabucayre / litexOnColorlightLab004
  basic example of litex on colorLight 5A-75B based on fpga_101/lab004
  ☆36Updated 2 years ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆96Updated 9 months ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆54Updated 7 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆90Updated 6 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆78Updated 3 years ago
• silicon-vlsi / VLSI-2024
  Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab.
  ☆11Updated 2 years ago
• RISCuinho / core
  **RISC**uinho - A scratch in the possibilities in the universe of microcontrollers
  ☆23Updated 3 years ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆172Updated 5 years ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆319Updated last month
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 5 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆70Updated 3 years ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆159Updated 7 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆41Updated 3 years ago
• iDoka / awesome-fpga-boards
  Second life for FPGA boards which can be repurposed to DYI/Hobby projects ..............................................................…
  ☆98Updated 4 years ago
• zxmarcos / huedeon-gpu
  FPGA GPU design for DE1-SoC
  ☆73Updated 3 years ago
• AEW2015 / fpga-colab
  FPGA examples on Google Colab
  ☆27Updated 4 months ago
• ChinaQMTECH / QM_XC7A100T_WUKONG_BOARD
  ☆35Updated last year
• Obijuan / RISC-V-FPGA
  RISC-V CPU for OpenFPGAs, in Icestudio
  ☆96Updated last year
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 4 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆160Updated 9 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆62Updated 2 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆54Updated 2 years ago