AngeloJacobo / RISC-VLinks
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
☆113Updated last year
Alternatives and similar repositories for RISC-V
Users that are interested in RISC-V are comparing it to the libraries listed below
Sorting:
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆119Updated 3 weeks ago
- Basic RISC-V Test SoC☆153Updated 6 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆145Updated 3 weeks ago
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- A demo system for Ibex including debug support and some peripherals☆78Updated 4 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 11 months ago
- SystemVerilog Tutorial☆177Updated 2 weeks ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆136Updated 5 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆54Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆99Updated this week
- ☆13Updated this week
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆50Updated 4 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆91Updated 4 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆100Updated 2 years ago
- RISC-V Nox core☆68Updated 3 months ago
- A simple implementation of a UART modem in Verilog.☆157Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆64Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆89Updated last year
- A Fast, Low-Overhead On-chip Network☆231Updated last week
- This repository contains the design files of RISC-V Single Cycle Core☆56Updated last year
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆64Updated 11 months ago
- Vector processor for RISC-V vector ISA☆129Updated 5 years ago
- RISC-V Verification Interface☆108Updated this week
- Curriculum for a university course to teach chip design using open source EDA tools☆111Updated 2 years ago
- RISC-V System on Chip Template☆159Updated 2 months ago