Reconfigurable Computing Lab, DESE, Indian Institiute of Science
☆33Jun 27, 2022Updated 3 years ago
Alternatives and similar repositories for I2SRV32-S-v1
Users that are interested in I2SRV32-S-v1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆34Jun 22, 2024Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Jun 22, 2024Updated last year
- A vision transformer based framework for classifying executable images as benign or malicious☆10Mar 19, 2024Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆149Oct 2, 2025Updated 8 months ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆14May 2, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- Baremetal softwares for TrivialMIPS platform☆11Aug 12, 2019Updated 6 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆30Feb 19, 2025Updated last year
- Synthesizable SystemVerilog IP-Core of the I2S Receiver☆10Jun 7, 2020Updated 6 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆86Oct 28, 2023Updated 2 years ago
- Simple RiscV core for academic purpose.☆23Apr 29, 2020Updated 6 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆48Jun 13, 2023Updated 3 years ago
- ☆25Jun 23, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- repository for a bandgap voltage reference in SKY130 technology☆44Jan 20, 2023Updated 3 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆34Jan 23, 2024Updated 2 years ago
- RISC-V microcontroller IP core for embedded, FPGA and ASIC applications☆200May 26, 2026Updated 3 weeks ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆67Nov 7, 2024Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆86Sep 17, 2022Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago
- A Verilog implementation of a processor cache.☆40Dec 29, 2017Updated 8 years ago
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Apr 18, 2025Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- 100 Days of RTL☆418Aug 15, 2024Updated last year
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆45Jul 11, 2025Updated 11 months ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆29Jul 17, 2025Updated 11 months ago
- Social Disatancing Monitor using yolov3 and DPU HW acceleration for Xilinx adaptive computing challenge 2020☆12Feb 17, 2023Updated 3 years ago
- Alternative compiler for the J1B embedded CPU☆15Oct 31, 2020Updated 5 years ago
- A Reconfigurable RISC-V Core for Approximate Computing☆130May 30, 2025Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆83Nov 26, 2020Updated 5 years ago
- BiSUNA framework specialized to compile for the Xilinx Alveo U50☆13Dec 3, 2020Updated 5 years ago
- ☆10Feb 8, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A RISC-V processor in system verilog☆12Jul 9, 2020Updated 5 years ago
- An FPGA design for simulating biological neurons☆18Jul 5, 2024Updated last year
- ☆19May 5, 2022Updated 4 years ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated 3 months ago
- RISC V 32 bit Base ISA Implementation.☆15May 28, 2024Updated 2 years ago
- My notes for DDR3 SDRAM controller☆54Feb 23, 2023Updated 3 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 9 years ago