Alternatives and similar repositories for I2SRV32-S-v1

Users that are interested in I2SRV32-S-v1 are comparing it to the libraries listed below

• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆49Updated 3 years ago
• RClabiisc / I2SRV32-V-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆29Updated last year
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• chinthacharan / DV-Interview-Prep-Guide
  Design Verification Engineer interview preparation guide.
  ☆38Updated 3 months ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆26Updated 2 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆126Updated last month
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆53Updated 5 years ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆26Updated 4 years ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆37Updated 3 years ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆91Updated last year
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆14Updated last year
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆115Updated last year
• avashist003 / SystemVerilog_Design_Verification
  Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
  ☆25Updated 3 years ago
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆18Updated 2 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆80Updated 4 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆63Updated last year
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆74Updated 4 years ago
• Noman-10xe / AXI-DMA-Verification
  Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
  ☆39Updated 4 months ago
• vlsiexcellence / Digital-ASIC-Design-Projects-
  Verilog Design, Simulation & Synthesis of Digital ASIC Projects
  ☆16Updated 2 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆65Updated last year
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆75Updated 6 years ago
• mbits-mirafra / UVMCourse
  Structured UVM Course
  ☆52Updated last year
• RClabiisc / I2SRV64-SS-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆27Updated last year
• IUST-Computer-Organization / LUMOS
  Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
  ☆48Updated 10 months ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• dineshannayya / riscduino_dcore
  ☆13Updated last year
• Devipriya1921 / VSDBabySoC_ICC2
  ☆14Updated 3 years ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆67Updated 3 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated 10 months ago