pulp-platform / trace_debuggerLinks
Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
☆19Updated last year
Alternatives and similar repositories for trace_debugger
Users that are interested in trace_debugger are comparing it to the libraries listed below
Sorting:
- ☆51Updated 3 weeks ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 3 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 months ago
- Yet Another RISC-V Implementation☆99Updated last year
- OmniXtend cache coherence protocol☆82Updated 7 months ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- ☆40Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- A Verilog Synthesis Regression Test☆37Updated 2 weeks ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆40Updated 2 years ago
- RISC-V processor tracing tools and library☆16Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆107Updated 4 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- ☆33Updated 3 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Updated 3 weeks ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Example of how to use UVM with Verilator☆34Updated 2 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago