pulp-platform / trace_debuggerLinks
Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
☆19Updated last year
Alternatives and similar repositories for trace_debugger
Users that are interested in trace_debugger are comparing it to the libraries listed below
Sorting:
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Platform Level Interrupt Controller☆40Updated last year
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated last week
- Consistency checker for memory subsystem traces☆21Updated 8 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- RISC-V processor tracing tools and library☆16Updated last year
- ☆29Updated last month
- ☆46Updated 3 weeks ago
- RISC-V Nexus Trace TG documentation and reference code☆51Updated 5 months ago
- Advanced Debug Interface☆15Updated 4 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- RISC-V Core Local Interrupt Controller (CLINT)☆26Updated last year
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated 3 weeks ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year
- RISC-V soft-core PEs for TaPaSCo☆19Updated 11 months ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆36Updated 2 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆35Updated last year
- RISC-V processor☆31Updated 3 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆20Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- SoCRocket - Core Repository☆37Updated 8 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 2 years ago