Alternatives and similar repositories for trace_debugger

Users that are interested in trace_debugger are comparing it to the libraries listed below

• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 5 years ago
• riscv / riscv-test-env
  ☆50Updated last month
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆54Updated 10 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated last month
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆102Updated 4 years ago
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆40Updated 2 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆32Updated 9 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 7 months ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated 2 weeks ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆86Updated 4 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 5 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• pulp-platform / trdb
  RISC-V processor tracing tools and library
  ☆16Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆76Updated last year
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆149Updated 2 weeks ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆67Updated 9 months ago
• riscvarchive / riscv-CMOs
  ☆89Updated 2 months ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆60Updated 5 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• carrv / carrv.github.io
  Workshop on Computer Architecture Research with RISC-V (CARRV)
  ☆41Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 2 weeks ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆98Updated last year