pulp-platform / trace_debuggerLinks
Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
☆19Updated last year
Alternatives and similar repositories for trace_debugger
Users that are interested in trace_debugger are comparing it to the libraries listed below
Sorting:
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆38Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- ☆47Updated last month
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆35Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- ☆33Updated 2 years ago
- ☆30Updated 2 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- Platform Level Interrupt Controller☆41Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated 11 months ago
- RISC-V processor tracing tools and library☆16Updated last year
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆33Updated 2 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ☆26Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 8 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- RISC-V soft-core PEs for TaPaSCo☆21Updated last year
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- Simple UVM environment for experimenting with Verilator.☆21Updated last month
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆18Updated last month
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- Simple runtime for Pulp platforms☆48Updated last week
- ☆31Updated this week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- ☆36Updated 2 years ago