pulp-platform / trace_debuggerLinks
Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
☆19Updated last year
Alternatives and similar repositories for trace_debugger
Users that are interested in trace_debugger are comparing it to the libraries listed below
Sorting:
- ☆51Updated 3 weeks ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 3 years ago
- RISC-V Nexus Trace TG documentation and reference code☆57Updated this week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- OmniXtend cache coherence protocol☆82Updated 7 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Updated 3 weeks ago
- ☆61Updated 5 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 months ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆108Updated 4 years ago
- Demo SoC for SiliconCompiler.☆62Updated this week
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 5 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- RISC-V processor tracing tools and library☆16Updated last year
- PCI Express controller model☆71Updated 3 years ago